Výsledky vyhledávání - "Annema, Anne J."

An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Autor: Bindra, Harijot Singh, Annema, Anne J., Louwsma, S.M., van Tuijl, Adrianus Johannes Maria, Nauta, Bram

Publikováno v: ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference

A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::6fdfbc6f4e5fe3f1f99f6e442e5c8e3f
https://research.utwente.nl/en/publications/7dbbb27e-0e8d-4320-924d-77e689bb6638

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Dependability investigation of wireless short range embedded systems: hardware platform oriented approach

Autor: Senouci, B., Kerkhoff, Hans G., Annema, Anne J., Bentum, Marinus Jan

Publikováno v: Journal of embedded systems, 3(1), 1-10. Science and Education Publishing

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of hundreds meters. Behind these embedded applications, a complex heterogeneous architecture is built. Moreover, thes

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::c4378a11885e832891efd778b7626cf4
https://research.utwente.nl/en/publications/dependability-investigation-of-wireless-short-range-embedded-systems-hardware-platform-oriented-approach(21c4a7f1-f2c7-404e-9a31-a68ec97d5ef2).html

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A 12b 1.7GS/s two-times interleaved DAC with

Autor: Olieman, E., Annema, Anne J., Nauta, Bram, Bal, Ankur, Singh, Pratap Narayan

Publikováno v: 2013 IEEE Asian Solid-State Circuits Conference, 81-84
STARTPAGE=81;ENDPAGE=84;TITLE=2013 IEEE Asian Solid-State Circuits Conference

A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::3821402cdb7a184eb8462ab83442f318
https://research.utwente.nl/en/publications/16436b22-8e76-44c5-b15b-e393cf4ed106

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45° light turning mirrors for hybrid integration of silica optical waveguides and photo-detectors

Autor: Çivitci, F., Sengo, G., Driessen, A., Pollnau, Markus, Hoekstra, Hugo, Annema, Anne J.

Publikováno v: 16th European Conference on Integrated Optics, ECIO 2012

For hybrid integration of an optical chip with an electronic chip with photo diodes and electronic processing, light must be coupled from the optical chip to the electronic chip. This paper presents a method to fabricate metal-free 45° quasi-total i

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::834a9e296cc91a97d19734906d6af0e4
https://research.utwente.nl/en/publications/45-light-turning-mirrors-for-hybrid-integration-of-silica-optical-waveguides-and-photodetectors(972a9a2d-d381-42c1-87d3-6a50d5d158a6).html

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A 0.0025mm2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS

Autor: Annema, Anne J., Goksun, G.

Publikováno v: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2012), 364-366
STARTPAGE=364;ENDPAGE=366;TITLE=IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2012)

A sub-1V bandgap voltage reference (BGVR) in 0.16μm CMOS is presented that circumvents the trade-off between area and power consumption in conventional sub-1V BGVR topologies. This circuit can be used in systems to generate reference voltages locall

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::12b09c4a24f5c3dfbda373264bcfb00f
https://research.utwente.nl/en/publications/1523c2a4-e527-4a54-9755-45e3c8ad3787

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The impact of CMOS scaling projected on a 6b full-Nyquist non-calibrated flash ADC

Autor: Veldhorst, P., Guksun, George, Annema, Anne J., Nauta, Bram, Buter, Berry, Vertregt, Maarten

Publikováno v: Prorisc 2009. 20th Annual Workshop on circuits, Systems and Signal Processing, 380-383
STARTPAGE=380;ENDPAGE=383;TITLE=Prorisc 2009. 20th Annual Workshop on circuits, Systems and Signal Processing

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::2d3c1171b3685ac07cc88f21fea10fa8
https://research.utwente.nl/en/publications/the-impact-of-cmos-scaling-projected-on-a-6b-fullnyquist-noncalibrated-flash-adc(363d8568-a8ce-4dfa-b210-0d572de4e3d4).html

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Design Equations for Class-E Power Amplifiers

Autor: Acar, M., Annema, Anne J., Nauta, Bram

Publikováno v: 17th Annual Workshop on Circuits Systems and Signal Processing (ProRISC)

In literature, it is widely accepted that the design of Class-E Power Amplifier (PA) with finite dc feed inductance requires a long iterative solution procedure. To avoid such iterative solution methods, analytical design equations should be known. T

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::2309903d3a7c40af10e9da883b930a37
https://research.utwente.nl/en/publications/0c579aea-6c4f-4c32-8a19-63c917578098

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A digital to analog converter

Autor: Westra, Jan R., Annema, Anne J.

A digital to analog converter for a multibit digital input signal has a set of conversion elements for the positive signal excursions and a set of conversion elements for the negative signal excursions. In each set the conversion elements are selecte

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::7ccbcaab6405cd8faa7fafe5ab5af456
https://research.utwente.nl/en/publications/a-digital-to-analog-converter(0aa42dfa-c428-486c-85d3-fc56f3dc1981).html

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