Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Annelies Vanderheyden"'
Autor:
Evi Vranken, D. Vanhaeren, Rafael Venegas, Paola Favia, Hu Liang, Ming Zhao, P. K. Kandaswamy, Stefaan Decoutere, Robert Langer, Marleen Van Hove, Annelies Vanderheyden, Yoga Saripalli
Publikováno v:
physica status solidi c. 13:311-316
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7df2d8eb8815bb2f6c64a5a9e9153f2
https://doi.org/10.1002/pssc.201510280
https://doi.org/10.1002/pssc.201510280
Autor:
D. Vanhaeren, Asen Asenov, Salvatore Maria Amoroso, Pieter Weckx, Jacopo Franco, Razaidi Hussin, Ben Kaczer, Louis Gerrer, Annelies Vanderheyden, Naoto Horiguchi
Publikováno v:
IEEE Transactions on Electron Devices. 61:3265-3273
This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05bb562882f6f1e0f2af21f3dad48647
https://doi.org/10.1109/ted.2014.2336698
https://doi.org/10.1109/ted.2014.2336698
Autor:
Marco Semicic, Naoto Horiguchi, Asen Asenov, Ben Kaczer, Pieter Weckx, Annelies Vanderheyden, D. Vanhaeren, Jacopo Franco, Liping Wang, Salvatore Maria Amaroso, Louis Gerrer, Jie Ding, Razaidi Hussin
Publikováno v:
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfc948cf4488ca13de0339291e663ce2
https://doi.org/10.1109/sispad.2015.7292281
https://doi.org/10.1109/sispad.2015.7292281
Autor:
Dave Reid, D. Vanhaeren, Salvatore Maria Amoroso, Pieter Weckx, Liping Wang, Ben Kaczer, Binjie Cheng, Asen Asenov, Naoto Horiguchi, Marco Simicic, Jacopo Franco, Annelies Vanderheyden, Razaidi Hussin, Louis Gerrer, Jie Ding
Publikováno v:
ESSDERC
This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::008fe4b3d264043f64d71365562a491f
https://doi.org/10.1109/essderc.2015.7324758
https://doi.org/10.1109/essderc.2015.7324758
Autor:
Razaidi Hussin, Jacopo Franco, Pieter Weckx, Salvatore Maria Amoroso, B. Kaczer, Louis Gerrer, Annelies Vanderheyden, Naoto Horiguchi, Asen Asenov, Liping Wang, D. Vanhaeren
Publikováno v:
2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).
The microelectronics industry faces important challenges in reducing technology development and circuit design times. This advocates the use of TCAD approaches to co-optimize circuits and device development. This paper presents the process of calibra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::635e3737d26a2ca7e49245b92bf13f0f
https://doi.org/10.1109/prime.2015.7251387
https://doi.org/10.1109/prime.2015.7251387
Autor:
S-G Lee, Kathy Barla, Pierre Eyben, Hugo Bender, Adam Brand, Geert Eneman, P. Storck, Sun-Ghil Lee, Naomi Yoshida, Hans Mertens, D. Vanhaeren, L.-A. Ragnarsson, Jacopo Franco, David P. Brunco, Paola Favia, Niamh Waldron, Nadine Collaert, Jerome Mitard, R. Olivier, Roger Loo, Liesbeth Witters, Xinliang Lu, Jianwu Sun, Hiroaki Arimura, Annelies Vanderheyden, S. Sonja, M. Vorderwestner, Alexey Milenin, Christa Vrancken, A. V-Y. Thean, Andriy Hikavyy, Naoto Horiguchi
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. Wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3923e3b669c015ad7cf6819abb727d7
https://doi.org/10.1109/vlsit.2014.6894391
https://doi.org/10.1109/vlsit.2014.6894391