Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Anirudh Mohan Kaushik"'
Autor:
Hiren D. Patel, Anirudh Mohan Kaushik
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:3318-3331
Predictable hardware cache coherence is a viable shared data communication mechanism between cores for multicore real-time platforms. Prior works have established that predictable hardware cache coherence protocols offer significant performance advan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49360c996631fdd31606cbf7d5032126
https://doi.org/10.1109/tcad.2021.3123056
https://doi.org/10.1109/tcad.2021.3123056
Publikováno v:
IEEE Transactions on Computers. 70:2098-2111
This article addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We propose a collection of predictable cache coherence protocols, which mandate the use of certain design invariants to ensur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::320df65c02a98ea0b71d0781be765bd8
https://doi.org/10.1109/tc.2020.3037747
https://doi.org/10.1109/tc.2020.3037747
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 18:1-25
Data-dependent memory accesses (DDAs) pose an important challenge for high-performance graph analytics (GA). This is because such memory accesses do not exhibit enough temporal and spatial locality resulting in low cache performance. Prior efforts th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4a70660d0ccf5d75f6994c94641ac87
https://doi.org/10.1145/3439803
https://doi.org/10.1145/3439803
Publikováno v:
RTAS
This work presents MapleBoard: a set of opensource hardware tools to implement predictable cache coherence protocols in hardware. MapleBoard consists of the following: (1) a novel domain-specific language (DSL) for specifying coherence protocols and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f2430417430226c72ea5c0103247102e
https://doi.org/10.1109/rtas52030.2021.00016
https://doi.org/10.1109/rtas52030.2021.00016
Autor:
Anirudh Mohan Kaushik, Hiren D. Patel
Publikováno v:
RTAS
Predictable hardware cache coherence is an attractive data communication mechanism between safety-critical tasks deployed on real-time multi-core platforms due to its predictability and high-performance benefits. However, from a worst-case analysis s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31104342b171cf12324b1991af2aec8d
https://doi.org/10.1109/rtas52030.2021.00017
https://doi.org/10.1109/rtas52030.2021.00017
Autor:
Anirudh Mohan Kaushik, Hiren D. Patel
Publikováno v:
DATE
We present SYNTHIA, an open and automated tool for synthesizing predictable and high-performance snooping bus-based cache coherence protocols for multi-core processors in multi-processor system-on-chips (MPSoCs) deployed in real-time systems. SYNTHIA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d33f2a6bb089553637cbb05ffb2ef677
https://doi.org/10.23919/date51398.2021.9474238
https://doi.org/10.23919/date51398.2021.9474238
Publikováno v:
ACM Transactions on Embedded Computing Systems. 17:1-25
We explore techniques to reverse-engineer DRAM embedded memory controllers (MCs), including page policies, address mapping, and command arbitration. There are several benefits to knowing this information: They allow tightening worst-case bounds of em
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::657b3301ffc00246f87a830944edbaaa
https://doi.org/10.1145/3274281
https://doi.org/10.1145/3274281
Publikováno v:
RTSS
Emerging embedded systems deployed in the automotive and avionics domains execute applications with different criticalities, comprising what is known as Mixed Criticality Systems (MCS). Applications in MCS often share data between tasks (coming from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1081269a592fb7a82ab2bb7ea76e1dd7
https://doi.org/10.1109/rtss46320.2019.00045
https://doi.org/10.1109/rtss46320.2019.00045
Publikováno v:
RTSS
We present CARP, a predictable and high-performance data communication mechanism for multi-core mixed-criticality systems (MCS). CARP is realized as a hardware cache coherence protocol that enables communication between critical and non-critical task
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fcf4c00988197616ceb6a062651d9737
https://doi.org/10.1109/rtss46320.2019.00044
https://doi.org/10.1109/rtss46320.2019.00044
Autor:
Anirudh Mohan Kaushik, Noah Wolfe, Noel Chalmers, Bradford M. Beckmann, Scott Moe, Ashwin M. Aji, Muhammad Amber Hassaan, Sooraj Puthoor
Publikováno v:
IISWC
General-Purpose Graphics Processing Units (GPGPUs) are employed in today's fastest supercomputers to accelerate a variety of scientific compute workloads. These workloads typically comprise of data-parallel mathematical kernels that are well suited f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::daefac063a156f13ae54846daa648559
https://doi.org/10.1109/iiswc47752.2019.9042134
https://doi.org/10.1109/iiswc47752.2019.9042134