Zobrazeno 1 - 10
of 56
pro vyhledávání: '"Anirudh Devgan"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1790-1802
Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ebd51fdced4f022eae30aaf00258ee9
https://doi.org/10.1109/tcad.2007.895797
https://doi.org/10.1109/tcad.2007.895797
Publikováno v:
Journal of Low Power Electronics. 3:28-35
Power gating is a very effective technique to reduce the subthreshold leakage by using sleep transistors to turn off the functional blocks or cells when they are not used. When the sleep transistors are turned on, the power grid may experience a huge
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b594972c91de559c693bd3567867d55
https://doi.org/10.1166/jolpe.2007.116
https://doi.org/10.1166/jolpe.2007.116
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1685-1695
In addition to traditional constraints on frequency, leakage current has emerged as a stringent constraint in modern processor designs. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield predict
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d37329e34fa10a7636144c5a7a24a56
https://doi.org/10.1109/tcad.2005.858351
https://doi.org/10.1109/tcad.2005.858351
Publikováno v:
Journal of Low Power Electronics. 1:172-181
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::872c6e07e0780e0dc2dcdd9a78d64e5e
https://doi.org/10.1166/jolpe.2005.026
https://doi.org/10.1166/jolpe.2005.026
Publikováno v:
IEEE Design and Test of Computers. 22:376-385
Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and ga
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54895c7c5511cb914d7875da1b14f34a
https://doi.org/10.1109/mdt.2005.89
https://doi.org/10.1109/mdt.2005.89
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:1661-1669
For optimizations like physical synthesis and static timing analysis, efficient interconnect delay and slew computation is critical. Since one cannot often afford to run asymptotic waveform evaluation (Pillage and Rohrer, 1990), constant time solutio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::363be2b746e1da16576dd3d17d3f8512
https://doi.org/10.1109/tcad.2004.837727
https://doi.org/10.1109/tcad.2004.837727
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:509-516
Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16f4ba9e0ce5c6c6d3f0d31d85fbfe0c
https://doi.org/10.1109/tcad.2004.825861
https://doi.org/10.1109/tcad.2004.825861
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20:90-104
Interconnect synthesis techniques, such as wire sizing and buffer insertion/sizing, have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works that study buffer inser
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba7052003aea03788cf9f9d4dd3323ed
https://doi.org/10.1109/43.905678
https://doi.org/10.1109/43.905678
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19:98-110
This paper presents a general method for computing transient sensitivities using both direct and adjoint methods in controlled explicit event driven simulation algorithms that employ piecewise linear device models. Sensitivity information provides fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93b55ef89672959dadf5c871f5c31634
https://doi.org/10.1109/43.822623
https://doi.org/10.1109/43.822623
Publikováno v:
DAC
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in global interconnect paths; however, existing techniques only optimize de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4da9057cdad537108a52c9035f6e34f1
https://doi.org/10.1109/43.806808
https://doi.org/10.1109/43.806808