Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Aniruddha N. Udipi"'
Publikováno v:
ISCA
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a large number of chips on every memory access -- this increases energy co
Autor:
Rajeev Balasubramonian, Naveen Muralimanohar, Norman P. Jouppi, Niladrish Chatterjee, Aniruddha N. Udipi, Al Davis
Publikováno v:
ISCA
DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single request activates thousands of bit-lines in many DRAM chips
Publikováno v:
ISPASS
Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system p
Autor:
Al Davis, Niladrish Chatterjee, Jung-Sik Kim, Aniruddha N. Udipi, Rajeev Balasubramonian, Manjunath Shevgoor
Publikováno v:
MICRO
Many of the pins on a modern chip are used for power delivery. If fewer pins were used to supply the same current, the wires and pins used for power delivery would have to carry larger currents over longer distances. This results in an "IR-drop" prob
Publikováno v:
ISCA
It is well-known that memory latency, energy, capacity, bandwidth, and scalability will be critical bottlenecks in future large-scale systems. This paper addresses these problems, focusing on the interface between the compute cores and memory, compri
Publikováno v:
HPCA
It is expected that future on-chip networks for many-core processors will impose huge overheads in terms of energy, delay, complexity, verification effort, and area. There is a common belief that the bandwidth necessary for future applications can on
Publikováno v:
HiPC
Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typically split into multiple banks and these banks are either connected thro
Autor:
Srihari Makineni, Li Zhao, Niti Madan, Donald Newell, Rajeev Balasubramonian, Naveen Muralimanohar, Aniruddha N. Udipi, Ravishankar Iyer
Publikováno v:
HPCA
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and