Zobrazeno 1 - 10
of 60
pro vyhledávání: '"Andrzej Krasniewski"'
Publikováno v:
1998 Annual Conference Proceedings.
Autor:
Marcin Dokowicz, Ewelina Dyląg, Tomasz Knopik, Andrzej Krasniewski, Emanuel Kulczycki, Kinga Kurowska-Wilczyńska, Jacek Lewicki, Malińska Krystyna, Michał Markuszewski, Katarzyna Sobótka-Demianowska, Katarzyna Walczyk-Matuszyk, Jadwiga Mirecka, Michał Wierzchoń
Publikováno v:
Adam Mickiewicz University-Omega-PSIR
Warsaw University of Technology-OmegaPSIR
National Information Processing Institute
Warsaw University of Technology-OmegaPSIR
National Information Processing Institute
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::58921192637aa998521678619a262ef6
https://ruj.uj.edu.pl/xmlui/handle/item/143790
https://ruj.uj.edu.pl/xmlui/handle/item/143790
Autor:
Georg Winckler, Hanne Smidt, Andrzej Krasniewski, Hannele Niemi, Giuseppe Silvestri, DUZ Verlags- und Medienhaus GmbH
BEST OF THE BOLOGNA HANDBOOK contains carefully selected articles from the EUA Bologna Handbook devoted to the most critical and pressing issues in European higher education. Since it was first published in 2006, the Handbook has consisted of a serie
Autor:
Andrzej Krasniewski
Publikováno v:
Microprocessors and Microsystems. 32:303-312
We propose a cost-efficient concurrent error detection (CED) scheme for finite state machines (FSMs) designed for implementation with embedded memory blocks (EMBs) available in today's SRAM-based FPGAs. The proposed scheme is proven to detect each pe
Autor:
Andrzej Krasniewski
Publikováno v:
Higher Education in Europe. 33:125-138
This article discusses the developments in doctoral training in Poland. The reasons for a rapid growth in the number of PhD students (by a factor of twelve from 1990 to 2005) are explained and the associated problems and challenges are presented. The
Autor:
Andrzej Krasniewski
Publikováno v:
Journal of Systems Architecture. 49:283-296
Testing delay faults in FPGAs differs significantly from testing delay faults in circuits whose combinational sections are represented as gate networks. Based on delay fault testability conditions, formulated in a form suitable for analysis of LUT-ba
Autor:
Andrzej Krasniewski
Publikováno v:
IFAC Proceedings Volumes. 36:195-200
We present necessary and sufficient conditions that must be satisfied by an irredundant logical path in a combinational subcircuit of LUT-based FPGAs, i.e. a path that can, under some delay assignment, detennine the speed of the circuit. A one-to-one
Autor:
Andrzej Krasniewski
Publikováno v:
IFAC Proceedings Volumes. 33:129-134
An application-dependent FPGA testing, i.e. testing of an FPGA configured to implement a user-defined function, must be performed to ensure correct operation of an FPGA-based system with regard to timing characteristics. Assuming application-dependen
Publikováno v:
IEEE Transactions on Appiled Superconductivity. 9:18-38
The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circui
Autor:
J. Woznicki, Andrzej Krasniewski
Publikováno v:
IEEE Transactions on Education. 41:237-246
To survive in the highly competitive environment, an engineering education institution must offer its students an attractive system of study. Essential features of such a system are flexibility and adaptability. Flexibility means that the system prov