Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Andrew Lukefahr"'
Publikováno v:
2021 IEEE Physical Assurance and Inspection of Electronics (PAINE).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2150e6133e016bf1445f2254ee76f479
https://doi.org/10.1109/paine54418.2021.9707698
https://doi.org/10.1109/paine54418.2021.9707698
Publikováno v:
ACM Transactions on Embedded Computing Systems. 18:1-21
Deep Neural Networks (DNNs) have become an essential component of various applications. While today’s DNNs are mainly restricted to cloud services, network connectivity, energy, and data privacy problems make it important to support efficient DNN c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1cfbafdf2203f3d11a49e39480b1f75
https://doi.org/10.1145/3358189
https://doi.org/10.1145/3358189
Publikováno v:
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE).
Field-Programmable Gate Arrays (FPGAs) are used almost everywhere, from smart-phones to datacenters. FPGA functionality is determined by the intellectual property (IP) encoded within a vendor-proprietary binary configuration file, or bitstream, that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98297812f70f21db7d650c5ad0a0e949
https://doi.org/10.1109/paine49178.2020.9337563
https://doi.org/10.1109/paine49178.2020.9337563
Publikováno v:
ITC
Security concerns for field-programmable gate array (FPGA) applications and hardware are evolving as FPGA designs grow in complexity, involve sophisticated intellectual properties (IPs), and pass through more entities in the design and implementation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5bac50f5d8c3b0b851425d1a2670070
https://doi.org/10.1109/itc44170.2019.9000145
https://doi.org/10.1109/itc44170.2019.9000145
Autor:
Mark Tehranipoor, Adib Nahiyan, Andrew Lukefahr, Grant Skipper, Martin Swany, Adam R. Duncan, Andrew Stern, Fahim Rahman
Publikováno v:
HOST
Security-critical field programmable gate array (FPGA) designs traditionally rely on bitstream encryption and hashing to prevent bitstream modifications and provide design authentication. Recent attacks to extract bitstream encryption keys, and resea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0899f7c7d07c32e8735509d07849d818
https://doi.org/10.1109/hst.2019.8741025
https://doi.org/10.1109/hst.2019.8741025
Autor:
Andrew Lukefahr, Reetuparna Das, Shruti Padmanabha, Thomas F. Wenisch, Ronald G. Dreslinski, Scott Mahlke, Faissal M. Sleiman
Publikováno v:
IEEE Transactions on Computers. 65:535-547
Heterogeneous multicore systems—comprising multiple cores with varying performance and energy characteristics—have emerged as a promising approach to increasing energy efficiency. Such systems reduce energy consumption by identifying application
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14cca81deee3f87e304310c6586b6b91
https://doi.org/10.1109/tc.2015.2419669
https://doi.org/10.1109/tc.2015.2419669
Publikováno v:
MICRO
Heterogenous chip multiprocessors (Het-CMPs) offer a combination of large Out-of-Order (OoO) cores optimized for high singlethreaded performance and small In-Order (InO) cores optimized for low-energy and area costs. Due to practical constraints, CMP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b89785108255501327f113e2ced04683
https://doi.org/10.1145/3123939.3123969
https://doi.org/10.1145/3123939.3123969
Publikováno v:
ISCA
As the size of Deep Neural Networks (DNNs) continues to grow to increase accuracy and solve more complex problems, their energy footprint also scales. Weight pruning reduces DNN model size and the computation by removing redundant weights. However, w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::14df93b29bdc75913cc2995e21a33602
https://doi.org/10.1145/3079856.3080215
https://doi.org/10.1145/3079856.3080215
Publikováno v:
MICRO
InOrder (InO) cores achieve limited performance because their inability to dynamically reorder instructions prevents them from exploiting Instruction-Level-Parallelism. Conversely, Out-of-Order (OoO) cores achieve high performance by aggressively spe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76505a82f5e353bf5e1621f54d237901
https://doi.org/10.1145/2830772.2830791
https://doi.org/10.1145/2830772.2830791
Autor:
Andrew Lukefahr, Thomas F. Wenisch, Scott Mahlke, Reetuparna Das, Shruti Padmanabha, Ronald G. Dreslinski
Publikováno v:
PACT
Heterogeneous architectures offer many potential avenues for improving energy efficiency in today's low-power cores. Two common approaches are dynamic voltage/frequency scaling (DVFS) and heterogeneous microarchitectures (HMs). Traditionally both app
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df08fc7dea4bfa559ab5e9283445c97b
https://doi.org/10.1145/2628071.2628078
https://doi.org/10.1145/2628071.2628078