Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Andrew D. Hilton"'
Publikováno v:
MICRO
Sprinting is a class of mechanisms that provides a short but significant performance boost while temporarily exceeding the thermal design point. We propose DynaSprint, a software runtime that manages sprints by dynamically predicting utility and mode
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd9292bd71bfd7fd95c57b08075c8b55
https://doi.org/10.1145/3352460.3358301
https://doi.org/10.1145/3352460.3358301
Publikováno v:
CompEd
Students in introductory programming courses struggle with how to turn a problem statement into code. We introduce a teaching technique, "The Seven Steps," that provides structure and guidance on how to approach a problem. The first four steps focus
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0e90d6cf275a3013fdd6cb207b1e52a
https://doi.org/10.1145/3300115.3309508
https://doi.org/10.1145/3300115.3309508
Publikováno v:
ITiCSE
Students in introductory programming courses struggle with how to turn a problem statement into code. We introduce a technique, ``The Seven Steps,'' that provides structure and guidance on how to approach a problem. The first four steps focus on devi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f11a3411d34ee30c4f6015da5dc12b8
https://doi.org/10.1145/3197091.3205807
https://doi.org/10.1145/3197091.3205807
Publikováno v:
ISPASS
Secure memory increases both the latency and energy required for memory accesses. To reduce these overheads, computer architects have sought to cache metadata on the processor chip, but placing metadata in a simple cache has not been as effective as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b207c96fde5f07385b555fe127e3f9da
https://doi.org/10.1109/ispass.2018.00012
https://doi.org/10.1109/ispass.2018.00012
Publikováno v:
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::667544cbef098c9a505fc0ed34c0cd3b
https://doi.org/10.1109/micro.2016.7783741
https://doi.org/10.1109/micro.2016.7783741
Publikováno v:
ISCA
We propose an ISA extension that decouples the data access and register write operations in a load instruction. We describe system and hardware support for decoupled loads. Furthermore, we show how compilers can generate better static instruction sch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e37219fda1be1bed0bd7221ec557f85e
https://doi.org/10.1109/isca.2016.43
https://doi.org/10.1109/isca.2016.43
Autor:
Andrew D. Hilton, Amir Roth
Publikováno v:
IEEE Computer Architecture Letters. 9:25-28
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any thread appear to occur in program order to all other threads. Out-of-order execution can violate load-load ordering. Multi-processors with out-of-order cores
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b20596b0a242e011609567e3b0c4c17
https://doi.org/10.1109/l-ca.2010.8
https://doi.org/10.1109/l-ca.2010.8
Publikováno v:
HPCA
In-order continual flow pipeline (iCFP) is an in-order pipeline that allows execution to flow around data cache misses. When a cache miss occurs, iCFP executes and speculatively retires miss-independent instructions. It saves miss-dependent instructi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d1bb3df286b7c7a93f115d43da653cc5
https://doi.org/10.1109/mm.2010.20
https://doi.org/10.1109/mm.2010.20
Publikováno v:
ISPASS
Although definition of single-program benchmarks is relatively straight-forward—a benchmark is a program plus a specific input—definition of multi-program benchmarks is more complex. Each program may have a different runtime and they may have dif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3253b014d9a529e1813d1c658774df1e
https://doi.org/10.1109/ispass.2015.7095786
https://doi.org/10.1109/ispass.2015.7095786
Publikováno v:
HPCA
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We describe and evaluate a more flexible register management scheme — refe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::002bfdca640003931205a690ffc17003
https://doi.org/10.1109/hpca.2012.6169033
https://doi.org/10.1109/hpca.2012.6169033