Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Andres Viveros"'
Publikováno v:
Algorithms, Vol 17, Iss 9, p 393 (2024)
This study examines the problem of minimizing the amount and distribution of time delays or latencies experienced by data as they travel from one point to another within a software-defined network (SDN). For this purpose, a model is proposed that see
Externí odkaz:
https://doaj.org/article/820375069b124df88ae2e16f5fa337d8
Autor:
Edgar A. Vega-Ochoa, Johana L. Silva-Cortes, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Jose E. Rayas-Sanchez, Andres Viveros-Wacher
Publikováno v:
IEEE Transactions on Electromagnetic Compatibility. 64:516-523
Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market commitments. Improvements in signaling
Publikováno v:
2022 IEEE International Conference on Automation/XXV Congress of the Chilean Association of Automatic Control (ICA-ACCA).
Autor:
Ismael Duron-Rosales, Nagib Hakim, Edgar A. Vega-Ochoa, Francisco E. Rangel-Patino, Jose E. Rayas-Sanchez, Andres Viveros-Wacher, Enrique Lopez-Miralrio
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 8:453-463
There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical
Publikováno v:
Mobile Web and Intelligent Information Systems ISBN: 9783031143908
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ee60567d51b205d6610edc3ce2cd5e9
https://doi.org/10.1007/978-3-031-14391-5_10
https://doi.org/10.1007/978-3-031-14391-5_10
Publikováno v:
IEEE Transactions on Microwave Theory and Techniques. 67:2143-2150
The demand and relevance of efficient analog fault diagnosis methods for modern RF and microwave-integrated circuits increase with the growing need and complexity of analog and mixed-signal circuitry. The well-established digital fault diagnosis meth
Autor:
Francisco E. Rangel-Patino, Edgar A. Vega-Ochoa, Nagib Hakim, Jose L. Chavez-Hurtado, Jose E. Rayas-Sanchez, Andres Viveros-Wacher
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38:733-740
As microprocessor design scales to the 10-nm technology and beyond, traditional pre- and post-silicon validation techniques are unsuitable to get a full system functional coverage. Physical complexity and extreme technology process variations severel
Autor:
Paulo Lopez-Meyer, Esdras Juarez-Hernandez, Andres Viveros-Wacher, Aaron Desiga-Orenday, Cesar A. Sanchez-Martinez
Publikováno v:
ITC
Post-Silicon system margin validation consumes a significant amount of time and resources. To overcome this, a reduced validation plan for derivative products has previously been used. However, a certain amount of validation is still needed to avoid
Publikováno v:
Cochrane Database Syst Rev
This is a protocol for a Cochrane Review (intervention). The objectives are as follows: To compare the effects of early intrauterine device (IUD) removal and conventional treatment, including antibiotic treatment (any concentration, frequency, durati
Autor:
Jose L. Chavez-Hurtado, Nagib Hakim, Andres Viveros-Wacher, Jose E. Rayas-Sanchez, Francisco E. Rangel-Patino
Publikováno v:
IEEE Transactions on Microwave Theory and Techniques. 65:3109-3115
There is an increasingly higher number of mixed-signal circuits within microprocessors. A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links is critical to provide a release qualific