A 64-channel back-gate adapted ultra-low-voltage spike-aware neural recording front-end with on-chip lossless/near-lossless compression engine and 3.3V stimulator in 22nm FDSOI

Autor: Franz Marcus Schuffny, Seyed Mohammad Ali Zeinolabedin, Richard George, Liyuan Guo, Annika Weise, Johannes Uhlig, Julian Meyer, Andreas Dixius, Stefan Hanzsche, Marc Berthel, Stefan Scholze, Sebastian Hoppner, Christian Mayr

Publikováno v: 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::71466048eb2ccfb1930d0496a4160b4f
https://doi.org/10.1109/a-sscc56115.2022.9980793

A 16-Channel Fully Configurable Neural SoC with 1.52W/Ch Signal Acquisition, 2.79W/Ch Real-time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22nm FDSOI

Autor: Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schuffny, Richard George, Florian Kelber, Heiner Bauer, Stefan Scholze, Stefan Hanzsche, Marco Stolba, Andreas Dixius, Georg Ellguth, Dennis Walter, Sebastian Hoppner, Christian Mayr

Publikováno v: IEEE Transactions on Biomedical Circuits and Systems

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific res

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::70db0c9b211ee540d418ffc3f0d944c8

Creating the Future

Autor: Andreas Dixius, Christian Mayr, Jim Garside, Stefan Scholze, Steve Furber, Felix Neumarker, Michael Hopkins, Johannes Partzsch, Marco Stolba, Florian Kelber, Dongwei Hu, Delong Shang, Mantas Mikaitis, David Clark, Stefan Schiefer, Gengting Liu, Sebastian Hoppner

Publikováno v: Clark, D, Dixius, A, Furber, S, Garside, J, Hopkins, M, Höppner, S, Hu, D, Kelber, F, Liu, G, Mayr, C, Mikaitis, M, Neumärker, F, Partzsch, J, Schiefer, S, Scholze, S, Shang, D & Stolba, M 2020, Creating the Future . in S Furber & P Bogdan (eds), SpiNNaker : A Spiking Neural Network Architecture . Now Publishers Inc, Boston-Delft, pp. 266-284 . https://doi.org/10.1561/9781680836530.ch8

In this chapter, we take a look into the future of this technology. First we survey interesting developments in hardware accelerators for SNNs and ANNs, but then we focus primarily on the second-generation SpiNNaker developments. Here we will refer t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::861ec8994d16457c4377761db8b61944
https://doi.org/10.1561/9781680836530.ch8

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip

Autor: Gengting Liu, David Lester, Mantas Mikaitis, Stefan Scholze, Steve Furber, Sebastian Hoppner, Delong Shang, Jim Garside, Andreas Dixius

Publikováno v: ARITH
2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)
Mikaitis, M, Lester, D, Shang, D, Furber, S, Liu, G, Garside, J, Scholze, S, Hoppner, S & Dixius, A 2018, ' Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip ', Paper presented at 25th IEEE Symposium on Computer Arithmetic, 25/06/18-27/06/18 pp. 37-44 . https://doi.org/10.1109/ARITH.2018.8464785

Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more $e^{x}$ components. SpiNNaker

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::90500a5170189d04471525036d93eaec
https://doi.org/10.1109/arith.2018.8464785

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

Autor: Matthias Eberlein, Steve Furber, Luis A. Plana, Sebastian Hoppner, Felix Neumarker, Johannes Partzsch, Andreas Dixius, Stephan Hartmann, Christian Mayr, Love Cederstroem, Steve Temple, Stefan Schiefer, Prateek Joshi, David Lester, Jim Garside, Bernhard Vogginger, Georg Ellguth, Stefan Scholze, Yexin Yan, Simon Davison

Publikováno v: ISCAS

We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This tec

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::128e088e46909e3fdc4cda16eda757d2
https://doi.org/10.1109/iscas.2017.8050396