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Autor:
Zhibin Ren, Josephine B. Chang, Munir D. Naeem, Judson R. Holt, Omer H. Dokumaci, Qingyun Yang, Kevin K. Chan, Arvind Kumar, John King, Xinlin Wang, John Yates, Cindy Wang, Jin Cho, Thomas S. Kanarsky, C. Ouyang, Andreas Bryant, Yongsik Moon, Ying Zhang, Andreas Gehring, Dae-Gyu Park, Marwan H. Khater, Michael A. Guillorn, Chung-Hsun Lin, Wilfried Haensch, Amlan Majumdar, Xi Li
Publikováno v:
2009 International Symposium on VLSI Technology, Systems, and Applications.
The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due