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pro vyhledávání: '"André DeHon"'
Autor:
Nachiket Kapre, André Dehon
Publikováno v:
International Journal of Reconfigurable Computing, Vol 2011 (2011)
Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating along graph edges. We can statially expose this struc
Externí odkaz:
https://doaj.org/article/48d938f3a33c4a45939ba24827857aeb
Autor:
Scott Hauck, André DeHon
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design— the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hard
Autor:
Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon
Publikováno v:
Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems.
Publikováno v:
FCCM
Fine-grained dataflow streaming between parallel compute operators provides both a simple form of concurrency and high performance operation. These streams are regularly used to support concurrency within HLS computations on the FPGA. We provide a co
Publikováno v:
FPT
Dedicated point-to-point wires (DW) can be used in place of a Packet-Switched Networks-on-a-Chip (PSNoC) for fast linking of separately-compiled FPGA blocks, providing higher bandwidth and performance with less area overhead without increasing compil
Autor:
André DeHon, Shlomo Hershkop, John Sonchack, Joel Hypolite, Nathan Dautenhahn, Jonathan M. Smith
Publikováno v:
CoNEXT
Restricting data plane processing to packet headers precludes analysis of payloads to improve routing and security decisions. DeepMatch delivers line-rate regular expression matching on payloads using Network Processors (NPs). It further supports pac
Autor:
André DeHon
Publikováno v:
IEEE Solid-State Circuits Magazine. 10:30-35
The TCFPGA Hall of Fame for FPGAs (field-programmable gate arrays) and Reconfigurable Computing recognizes the most significant peer-reviewed publications in the field, highlights key contributions, and represents the body of knowledge that has accum
Publikováno v:
IEEE Design & Test. 34:54-62
Editor’s note: This article describes a method to continuously monitor paths delays in an operational FPGA design and to improve slow paths by incremental partial reconfiguration. Since online delay measuring is more accurate than design time estim
Autor:
André DeHon
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 13:1-2