Zobrazeno 1 - 10
of 21
pro vyhledávání: '"An L. Steegen"'
Autor:
Arifuzzaman (Arif) Sheikh, J. Chen, Michael V. Aquilino, Mukesh Khare, James Chingwei Li, Weipeng Li, X. Chen, Laegu Kang, G. Massey, J. Sudijono, An L. Steegen, Vijay Narayanan, Jin-Ping Han, M. Zaleski, Rashmi Jha, Haoren Zhuang, M. Chowdhury, C. Reddy, Douglas D. Coolbaugh, Yi-Wei Lee, Michael P. Chudzik, Kenneth J. Stein, Zhenrong Jin, Shesh Mani Pandey, D. Tekleab, S. Samavedam, Christopher V. Baiocco, Haining Yang, Deleep R. Nair, JiYeon Ku, Chandrasekharan Kothandaraman, Craig S. Lage, Jaeger Daniel, R. Mo, C. Hobbs, S. Kalpat, Da Zhang, Naim Moumen, Nam-Sung Kim, S. Kirshnan, J. Wallner, X. Wang, R. Lindsay, Melanie J. Sherony, Aaron Thean, Young Way Teh
For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ad4bb3545ca27a0a35b2cac57515af2c
https://doi.org/10.1109/vlsit.2008.4588573
https://doi.org/10.1109/vlsit.2008.4588573
Autor:
Anda Mocuta, Min Yang, Keith A. Jenkins, Raquel T. Anderson, Paul Ronsheim, An L. Steegen, Jack O. Chu, Meikei Ieong, Byoung Hun Lee, V. Mazzeo, S. Christansen, K.K. Chan, H. Chen, P. Oldiges, T. Kanarsky, Kam-Leung Lee, S.J. Koester, Kern Rim, John A. Ott, Hon-Sum Philip Wong, Patricia M. Mooney, F. Cardone, Huilong Zhu, Ronnen Andrew Roy, Diane C. Boyd, Dan Mocuta
Publikováno v:
Solid-State Electronics. 47:1133-1139
Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern day’s CMOS technology. Significant mobility and curren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d27ced5d6d327ae962a6f6035aa37d11
https://doi.org/10.1016/s0038-1101(03)00041-8
https://doi.org/10.1016/s0038-1101(03)00041-8
Autor:
Melanie J. Sherony, Siddarth A. Krishnan, Z. J. Yang, J. Sudijono, Y. M. Lee, S. Han, N. Kusunoki, Xusheng Wu, G. Yang, Yue Hu, An L. Steegen, Y-W. Teh, Franck Arnaud, R. Kirshnan, Joseph F. Shepard
Publikováno v:
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).
This paper presents the advanced I/O device design for 32nm Hi-K Metal Gate technology with multi-high operation voltages. Process optimization work is done on the I/O composite gate dielectric stack to improve TDDB Vmax. By using advanced junction e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcc6636619f9c59b9b0f9fe28a3af608
https://doi.org/10.1109/edssc.2010.5713769
https://doi.org/10.1109/edssc.2010.5713769
Autor:
Melanie J. Sherony, J. Liang, M. Voelker, Myung-Hee Na, Jaeger Daniel, Kathy Barla, Y. Goto, G. Yang, Katsura Miyashita, Frank Scott Johnson, J.H. Park, R. Sampson, Jenny Lian, Kenneth J. Stein, JiYeon Ku, Christophe Bernicot, Knut Stahrenberg, S. Miyake, J. Sudijono, Haoren Zhuang, Li-Hong Pan, Ricardo A. Donaton, Martin Ostermayr, Gen Tsutsui, Manfred Eller, Richard A. Wachnik, S. Kohler, K. Kim, Wai-kin Li, Christian Wiedholz, M. Celik, Atsushi Azuma, An L. Steegen, T. Shimizu, Anda Mocuta, J.-P. Han, E. Kaste, H. van Meer, Masafumi Hamaguchi, Deleep R. Nair, N-S. Kim, Franck Arnaud, W. Neumueller, D. Chanemougame
Publikováno v:
Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ced71a741b8bf85c300152efdb2927b
https://doi.org/10.7567/ssdm.2010.c-6-5l
https://doi.org/10.7567/ssdm.2010.c-6-5l
Autor:
K. Strahrenberg, M. Lipinski, R. Augur, K. Kang, S. ElGhouli, Nam-Sung Kim, Manfred Eller, Frank Scott Johnson, Kazuya Ohuchi, M. Sekine, Katsura Miyashita, Masafumi Hamaguchi, S. Uchimura, S. Miyaki, Qintao Zhang, J. Sudijono, Deleep R. Nair, Paulo Ferreira, JiYeon Ku, Martin Ostermayr, J-H. Park, S. Kohler, Franck Arnaud, Ron Sampson, Aaron Thean, Young Way Teh, Fumiyoshi Matsuoka, Richard Lindsay, Jenny Lian, J. Bonnouvrier, J.-P. Han, An L. Steegen
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5bf65bdb19ddca923a6de57aadabae95
https://doi.org/10.1109/iedm.2009.5424255
https://doi.org/10.1109/iedm.2009.5424255
Autor:
M. Hatzistergos, Christian Pacha, Haoren Zhuang, Melanie J. Sherony, Yong Meng Lee, T.J. Tang, S. Han, S. Samavedam, Jens Haetty, Sun-OO Kim, Martin Ostermayr, R. Divakaruni, V.-Y. Theon, Weipeng Li, Kenneth J. Stein, Michael P. Chudzik, Haizhou Yin, X. Chen, Richard Lindsay, J.-P. Han, M. Chowdhury, Jaeger Daniel, Naim Moumen, Dae-Gyu Park, Nam-Sung Kim, Kisang Kim, Manfred Eller, Dominic J. Schepis, Rainer Loesing, Mukesh Khare, J. Chen, K. von Arnim, An L. Steegen, Thomas S. Kanarsky, Vijay Narayanan, W. Yan, Klaus Schruefer
Publikováno v:
2009 International Symposium on VLSI Technology, Systems, and Applications.
This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85726ae47609ee2928b18dfa8334b007
https://doi.org/10.1109/vtsa.2009.5159305
https://doi.org/10.1109/vtsa.2009.5159305
Autor:
Liyang Song, Franck Arnaud, Voon-Yew Thean, Yue Liang, Jie Chen, Jaeger Daniel, Huiming Bu, Philip J. Oldiges, Melanie J. Sherony, An L. Steegen, Joyce C. Liu, Dechao Guo, Michael P. Chudzik, Kathryn T. Schonenberg, Pranita Kulkarni, Mukesh Khare, William K. Henson, Unoh Kwon
Publikováno v:
MRS Proceedings. 1194
For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae0b5601f231fb823a7e0f5c61c0d67c
https://doi.org/10.1557/proc-1194-a04-02
https://doi.org/10.1557/proc-1194-a04-02
Autor:
J. Pape, Nam-Sung Kim, Martin Ostermayr, Deleep R. Nair, Melanie J. Sherony, Craig S. Lage, Jaeger Daniel, Franck Arnaud, Y. Gao, Deok-Hyung Lee, H.S. Yang, C. Schiller, X. Chen, S. Stiffler, An L. Steegen, Kenneth J. Stein, J. Sudijono, Christopher V. Baiocco, Haoren Zhuang, Robert C. Wong, Y. Takasu, Ho-Kyu Kang, Sayeed A. Badrudduza, J. Wallner, Laegu Kang, James Chingwei Li, Aaron Thean, Y.W. Teh, L. Zhuang, R. Hasumi, S. Samavedam, D.P. Sun, Mukesh Khare
Publikováno v:
2008 IEEE International Electron Devices Meeting.
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bcc347a597544ead57bce41996b65ef0
https://doi.org/10.1109/iedm.2008.4796660
https://doi.org/10.1109/iedm.2008.4796660
Autor:
Sanjay Natarajan, An L. Steegen
Publikováno v:
2007 IEEE International Electron Devices Meeting.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3282c65eb36b9970fa2161a238eb92c1
https://doi.org/10.1109/iedm.2007.4418920
https://doi.org/10.1109/iedm.2007.4418920
Autor:
Anda Mocuta, M. Angyal, An L. Steegen, Vidhya Ramachandran, T. Hook, Dan Moy, Douglas D. Coolbaugh, Percy V. Gilbert
Publikováno v:
2007 IEEE International Electron Devices Meeting.
A common platform technology at 65 nm is described. The platform consists of a low-power CMOS base technology with a broad menu of optional features including high- performance passive devices, standard cell libraries, SRAM compilers and a process de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8393053c3c2a00dca5a348521288a69
https://doi.org/10.1109/iedm.2007.4418917
https://doi.org/10.1109/iedm.2007.4418917