Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Amit Nahar"'
Autor:
Yiorgos Makris, Amit Nahar, Constantinos Xanthopoulos, Sirish Boddikurapati, Deepika Neethirajan
Publikováno v:
DATE
To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure
Publikováno v:
VTS
This special session will discuss how machine learning can transform test. The first talk will review the key challenges and will argue whether contemporary tools, such as deep learning, could offer any advantages over traditional methods. The second
Autor:
Constantinos Xanthopoulos, Sirish Boddikurapati, Ali Ahmadi, Bob Orr, Amit Nahar, Yiorgos Makris
Publikováno v:
ISCAS
Post silicon trimming is extensively used to counter the effects of manufacturing process variation on certain critical electrical parameters of an integrated circuit (IC). Usually, trimming is performed iteratively by adjusting the resistance value
Autor:
Ali Ahmadi, John Carulli, Ke Huang, Bob Orr, Haralampos-G. Stratigopoulos, Amit Nahar, Yiorgos Makris, Michael F. Pas
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩
International audience; Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::58abd8a68d760a8ed2f53145dc671b2b
https://hal.archives-ouvertes.fr/hal-02980993/document
https://hal.archives-ouvertes.fr/hal-02980993/document
Publikováno v:
ICCAD
We introduce a machine learning approach for distinguishing between integrated circuits fabricated in a ratified facility and circuits originating from an unknown or undesired source based on parametric measurements. Unlike earlier approaches, which
Publikováno v:
ITC
Since 2004, Texas Instruments and Portland State University have collaborated to develop and deploy test data analytical methods for use in a variety of applications, including quality screening, burn-in minimization, high cost test replacement and/o
Publikováno v:
ITC
Location Averaging is a nearest electrical neighbor method of Statistical Outlier Screening (SOS) for screening outliers from probe test data used at Texas Instruments (TI). Location Averaging is sensitive to variances, not only from die parametrics,
Publikováno v:
ITC
We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, ba
Autor:
Bob Orr, Amit Nahar, Michael F. Pas, Ali Ahmadi, Haralampos-G. Stratigopoulos, Yiorgos Makris
Publikováno v:
IEEE International Symposium on Circuits and Systems
IEEE International Symposium on Circuits and Systems, May 2016, Montreal, Canada. ⟨10.1109/ISCAS.2016.7527386⟩
ISCAS
IEEE International Symposium on Circuits and Systems, May 2016, Montreal, Canada. ⟨10.1109/ISCAS.2016.7527386⟩
ISCAS
Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::745d1d39fd0722e6b7bcccac8d1135be
https://hal.sorbonne-universite.fr/hal-01359613
https://hal.sorbonne-universite.fr/hal-01359613
Publikováno v:
VTS
We introduce a methodology for dynamically selecting whether to subject a wafer to a complete or a reduced probe-test flow, while ensuring that the concomitant test cost savings do not compromise test quality. The granularity of this decision is at t