Zobrazeno 1 - 10
of 46
pro vyhledávání: '"Amir Masoud Gharehbaghi"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:2990-2999
As the number of transistors in the fabricated circuits becomes extremely larger, not only single stuck-at faults, but also multiple stuck-at faults (MSAFs) are likely to happen in the circuits, especially for the large-scale circuit. Multiple faults
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1770-1780
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:1517-1530
This paper presents an energy- and area-efficient architecture for approximated discrete cosine transform (DCT). Due to the good compression ability, DCT is widely exploited in signal processing. However, it is computationally intensive especially fo
Publikováno v:
DATE
Engineering Change Order (ECO) and logic debugging problems where multiple locations in the circuit must be modified are formulated with Quantified Boolean Function (QBF) and set-sovering techniques. The formulation is based on the fanin selection me
Publikováno v:
ISQED
Recently, the opportunities of parallel computing are expanding rapidly in various applications including neural networks and machine learning. It is, however, not at all straightforward to develop an efficient algorithm for each parallel computing e
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:1063-1074
As fabricated circuitry becomes larger and denser, the modern industrial automatic test pattern generation techniques, which focus on the detection of single faults, become more likely to overlook multiple (simultaneous) faults. Although there are ex
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :685-696
Publikováno v:
VLSI-SoC
Approximate computing can be applied to error-tolerant applications, by trading off accuracy for lower power consumption, shorter delay and smaller area. In this paper, we focus on the approximate arithmetic circuit design especially targeting combin
Publikováno v:
ISCAS
Mapping of large systems/computations on multiple chips/multiple cores needs sophisticated compilation methods. In this demonstration, we present our compiler tools for multi-chip and multi-core systems that considers communication architecture and t
Publikováno v:
ISCAS
This paper proposes methods to get a minimally rectified logic circuit equivalent to a new specification. One of the proposed methods can deal with multiple target signals to be modified at the same time. Moreover, a graph-cut based method is propose