Zobrazeno 1 - 10 of 10 pro vyhledávání: '"Amat Bertran, Esteve"'
1
Statistical Lifetime Analysis in Memristive Crossbar
Autor: Pouyan, Peyman, Amat Bertran, Esteve, Rubio Sola, Jose Antonio
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
Universitat Jaume I
Emerging devices for future memory technologies have attracted great attention recently. Memristors are one of the most favorable such devices, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits th
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::0b6aa17cca874448a0d444b9c90a54a2
https://hdl.handle.net/2117/27219
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2
FinFET and III-V/Ge technology impact on 3T1D cell behavior
Autor: Amat Bertran, Esteve, Calomarde Palomino, Antonio, Almudever, Carmen G., Aymerich Capdevila, Nivard, Canal Corretger, Ramon, Rubio Sola, Jose Antonio
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
Universitat Jaume I
In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors)
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::8703cf31fa05cc6516811b20e81a75b5
https://hdl.handle.net/2117/26567
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3
SRAM lifetime improvement by using adaptive proactive reconfiguration
Autor: Pouyan, Peyman, Amat Bertran, Esteve, Rubio Sola, Jose Antonio
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design strategies at the Nanoscale circu
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::f0c0d900608885fa2eb00deaf23fe3d1
https://hdl.handle.net/2117/16297
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4
Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm
Autor: Amat Bertran, Esteve, García Almudéver, Carmen, Aymerich Capdevila, Nivard, Canal Corretger, Ramon|||0000-0003-4542-204X, Rubio Sola, Jose Antonio|||0000-0003-1625-1472
Publikováno v: Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Best DCIS Paper Award 2012 3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present signific
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::4da03ac96bc34b18650976665a3ee4c4
https://hdl.handle.net/2117/20163
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5
Proactive reconfiguration, a methodology for extending SRAM lifetime
Autor: Pouyan, Peyman, Amat Bertran, Esteve, Rubio Sola, Jose Antonio
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
Universitat Jaume I
The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique and furthermore it takes in
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::b79c2437b9163c2e5c0a4edeabb059bf
http://hdl.handle.net/2117/27160
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6
Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime
Autor: Rubio Sola, Jose Antonio|||0000-0003-1625-1472, Amat Bertran, Esteve, Pouyan, Peyman
Publikováno v: Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introdu
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::fd79e82dfbdeca731c1f456486b378bc
http://hdl.handle.net/2117/16582
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8
Integration of vertical Single Electron Transistor into CMOS technology
Autor: Moral Cejudo, Alberto Jose del
Publikováno v: TDX (Tesis Doctorals en Xarxa)
TDR. Tesis Doctorales en Red
instname
Dipòsit Digital de Documents de la UAB
Universitat Autònoma de Barcelona
Aquesta tesi presenta les investigacions realitzades cap a la integració de transistors verticals d’un sol electró (SET) en tecnologia metall-òxid-semiconductor complementari (CMOS). Dues de les principals motivacions de la indústria de semicon
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::2ce9abc221f1cbac6e03ee5d7bcb96ec
http://hdl.handle.net/10803/673762
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9
Statistical analysis and design of subthreshold operation memories
Autor: Rana, Manish
Publikováno v: TDX (Tesis Doctorals en Xarxa)
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
TDR. Tesis Doctorales en Red
instname
This thesis presents novel methods based on a combination of well-known statistical techniques for faster estimation of memory yield and their application in the design of energy-efficient subthreshold memories. The emergence of size-constrained Inte
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::f130cab764234e2594349e5b9fc776f6
https://hdl.handle.net/2117/9639510803/396376
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10
Reliability-aware memory design using advanced reconfiguration mechanisms
Autor: Pouyan, Peyman
Publikováno v: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
TDX (Tesis Doctorals en Xarxa)
TDR. Tesis Doctorales en Red
instname
Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achie
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::48997a3cc31bba54b1d8028de4ad0345
http://hdl.handle.net/2117/95998
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