Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Amaresh Pangal"'
Autor:
Y. Ye, Mark A. Anders, Sanu Mathew, Krishnamurthy Soumyanath, G. Dermer, Vivek De, Siva G. Narendra, S. Borkar, Dinesh Somasekhar, S. Thompson, V. Veeramachaneni, E. Seligman, James W. Tschanz, Ram Krishnamurthy, Vasantha Erraguntla, Nitin Borkar, M.R. Stan, V. Govindarajulu, Amaresh Pangal, B.A. Bloechel, Sriram R. Vangal, H. Wilson
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1421-1432
A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS tech
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::736d5cc82f3302f183f8978b5e8bce24
https://doi.org/10.1109/jssc.2002.803944
https://doi.org/10.1109/jssc.2002.803944
Autor:
Sriram R. Vangal, Amaresh Pangal, H. Wilson, B. Bloechel, Vasantha Erraguntla, V. Govindarajulu, E. Seligman, Siva G. Narendra, G. Dermer, R. Mooney, Rajendran Nair, A. Keshavarzi, Vivek De, Nitin Borkar, M. Haycock, S. Borkar
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A router chip, that incorporates on-chip forward body biasing capability with 2% area overhead, achieves 1 GHz operation at 1.1 V supply in a 150 nm logic technology, compared to 1.25 V required for the original design having no body bias. Switching
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8816032d6e4f6c2e2590e64ec74024d
https://doi.org/10.1109/isscc.2002.993040
https://doi.org/10.1109/isscc.2002.993040
Autor:
J. Tschanz, R. Krishnamurthy, V. Govindarajulu, Dinesh Somasekhar, Vasantha Erraguntla, Mark A. Anders, M.R. Stan, S. Borkar, B. Bloechel, Nitin Borkar, V. Veeramachaneni, Amaresh Pangal, G. Dermer, Y. Ye, S. Thompson, Siva G. Narendra, H. Wilson, Vivek De, E. Seligman, Sriram R. Vangal
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A 32 b integer execution core implements 12 instructions. Circuit and body bias techniques together increase the core clock frequency to 5 GHz. In a 130 nm six-metal dual-V/sub T/ CMOS process, the 2.3 mm/sup 2/ prototype contains 160 k transistors,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94e0323b4a78816fb2a2f85a7c04cb32
https://doi.org/10.1109/isscc.2002.993107
https://doi.org/10.1109/isscc.2002.993107
Autor:
E. Seligman, V. Govindarajulu, J.D. Prijic, G. Dermer, V. Eriaguntla, Nitin Borkar, Amaresh Pangal, Rajendran Nair, L. Rankin, H. Wilson, Sriram R. Vangal, C.S. Browning
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
A 28.5 GB/s data router enables a terabits/s bandwidth network. The 6.6M transistor 0.18 /spl mu/m 1.3 V 15 W CMOS LSI has three clocking domains that synchronize data through four 1.06 GB/s links, a B-port crossbar, and five point-to-point links of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0244a5ae029eb9bc5d99764740cd7414
https://doi.org/10.1109/isscc.2001.912614
https://doi.org/10.1109/isscc.2001.912614