Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Alvernon Walker"'
Autor:
Willie L. Brown, Ibibia Dabipi, Dinesh Sharma, Lei Zhang, Weiwei Zhu-Stone, Lanju Mei, Alvernon Walker, Tiara T. Cornelius, Jason Cornelius, Urban Wiggins, Etahe Johnson, Lakeisha Harris, John P. Murray, Enrique Jackson, Terence H. Fontaine, Linda B. Hayden
Publikováno v:
2022 IEEE Frontiers in Education Conference (FIE).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcca3ba59f3068ea62f38563d0d1be62
https://doi.org/10.1109/fie56618.2022.9962439
https://doi.org/10.1109/fie56618.2022.9962439
Autor:
Willie L. Brown, Ibibia Dabipi, Dinesh Sharma, Lei Zhang, Weiwei Zhu-Stone, Lanju Mei, Alvernon Walker, Tiara T. Cornelius, Jason Cornelius, Urban Wiggins, Etahe Johnson, Lakeisha Harris, John P. Murray, Enrique Jackson, Terence H. Fontaine, Linda B. Hayden
Publikováno v:
2022 IEEE Frontiers in Education Conference (FIE).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d96d739c761d78dd2614c0072f97eb1
https://doi.org/10.1109/fie56618.2022.9962413
https://doi.org/10.1109/fie56618.2022.9962413
Autor:
alvernon walker
Multiplication and addition determine the performance of general and special purpose processors because they are fundamental arithmetic functions. A variety of architectural realizations are needed for these functions to support the range of tradeoff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::410ce4fe464c1f229298e7f49c400493
https://doi.org/10.22541/au.166110301.18377143/v1
https://doi.org/10.22541/au.166110301.18377143/v1
Autor:
Evelyn Sowells-Boone, Alvernon Walker
Publikováno v:
Electrical Engineering : An International Journal. 5:01-07
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95c858145c4b0c6e95ba59aa69319ea0
https://doi.org/10.5121/eeij.2018.5101
https://doi.org/10.5121/eeij.2018.5101
Autor:
Evelyn Sowells-Boone, Alvernon Walker
Publikováno v:
Advances in Intelligent Systems and Computing ISBN: 9783030011765
A binary shift-add multiplier with a variable multiplication completion time that ranges from 1 to n clock cycles, where n is the number of bits in the input operands, is presented. The number of cycles required for this multiplier equals the number
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9743eb991edea77166150d8d291fe5ff
https://doi.org/10.1007/978-3-030-01177-2_99
https://doi.org/10.1007/978-3-030-01177-2_99
Autor:
Alvernon Walker
A base-4 leading zero detector (LZD) design is proposed in this paper. The design is similar to the approach originally proposed by V.G. Oklobdzija with a different technique. The circuit modules used in the base-4 LZD approach are designed and sever
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1b0b4eb772df923839cf1118399239b9
Autor:
Alvernon Walker, P.K. Lala
Publikováno v:
VLSI Design, Vol 12, Iss 4, Pp 527-536 (2001)
This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3d929caa228b373e024b600a71101b52
https://doaj.org/article/bcc3950eeefe4d41b27ef461521c26ba
https://doaj.org/article/bcc3950eeefe4d41b27ef461521c26ba
Publikováno v:
VLSI Design, Vol 7, Iss 2, Pp 151-161 (1998)
A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3c10f5847ca03dbda18de2695dbc6d00
https://doaj.org/article/3eb3c841301e42b789855568f9040a25
https://doaj.org/article/3eb3c841301e42b789855568f9040a25
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