Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Allison C. Rector"'
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2011:001596-001620
3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint.
Publikováno v:
ECS Transactions. 25:117-120
As the technology nodes shrink, device makers are running into barriers with traditional post etch process flows. In the back-end-of-line (BEOL), the porous low-k materials can be damaged by the etch chemistries, the dry ash plasmas and the subsequen