Transparent varnishes on copper alloys dating from the 19th century: characterization and identification strategies

Autor: Julie Schröter, Aline Michel, Sigrid Mirabaud, Laura Brambilla, Celine Paris, Ludovic Bellot-Gurlet

Publikováno v: Metal 2019. Proceedings of the interim meeting of the ICOM-CC metals working group
Claudia Chemello; Laura Brambilla; Edith Joseph. Metal 2019. Proceedings of the interim meeting of the ICOM-CC metals working group, pp.58-66, 2019, 978-92-9012-458-0
HAL

International audience; Many varnished copper-based artefacts dating from the 19th century can be found in museum collections. Although conservators deal on a daily basis with these surface finishes, few studies on this topic have been conducted duri

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::602d1d9aa5de4469003b3ec93078a97a
https://hal.archives-ouvertes.fr/hal-02382715/document

Timing Closure Management based on Delay Bound Determination

Autor: Azemard, Nadine, Aline, Michel, Maurine, Philippe, Auvergne, Daniel

Publikováno v: IFIP International Conference on Very Large Scale Integration-The Global System On Chip Design & CAD Conference
VLSI-SoC: Very Large Scale Integration-System-on-Chip
VLSI-SoC: Very Large Scale Integration-System-on-Chip, Dec 2001, Montpellier, France. pp.430-434

International audience; In this paper we present a method to determine the feasibility of delay constraint imposed on circuit path. This is of prime importance in minimizing the number of iterations when satisfying performance constraints in IC desig

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::0dd3bd130be958f0eea7e8e5e689c0ca
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239452

Upper and Lower bound Determination of delay on Critical Path

Autor: Aline, Michel, Azemard, Nadine, Auvergne, Daniel

Publikováno v: 15th Design of Circuits and Integrated Systems Conference
DCIS: Design of Circuits and Integrated Systems
DCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.543-547

International audience; Based on a path delay profiling tool we propose in this paper a method to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with the transistor sizing condition

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::25b4c5cccf43a0ef9318b197983465f8
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239437

Satisfaction of Delay/Power Constraints by Iterative Gate Sizing

Autor: Azemard, Nadine, Aline, Michel, Auvergne, Daniel

Publikováno v: 9th International Workshop on Power and Timing Modeling Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1999, Kos, Greece. pp.325-334

International audience; This paper adresses the problem of satisfying delay/power constraints using a post layout iterative gate sizing. Path sizing procedure is defined with a realistic evaluation of gate delay and power and an accurate estimation o

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::ccefedda9af7b13252be5cd31e20861b
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00244003

A New Tool for Path Performance Optimization

Autor: Cremoux, Séverine, Azemard, Nadine, Aline, Michel, Auvergne, Daniel

Publikováno v: International Workshop on IP Based Synthesis and System Design
International Workshop on IP Based Synthesis and System Design, Dec 1998, Grenoble, France. pp.175-179

International audience; Critical path control constitutes one of the fundamental step in circuit design and optimization. Based on an incremental path search algorithm we address the problem of delay performance driven path classification. A specific

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::b4ca5104e787e12306bab9486532b40a
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241408