Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Ali G. Saidi"'
Autor:
Ali G. Saidi, Satish Narayanasamy, Vaibhav Gogte, Aasheesh Kolli, Stephan Diestelhorst, Peter M. Chen, Thomas F. Wenisch
Publikováno v:
ISCA
The commercial release of byte-addressable persistent memories, such as Intel/Micron 3D XPoint memory, is imminent. Ongoing research has sought mechanisms to allow programmers to implement recoverable data structures in these new main memories. Ensur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7f79ee2cef492fb39269802bdd2474df
https://doi.org/10.1145/3140659.3080229
https://doi.org/10.1145/3140659.3080229
Publikováno v:
ASPLOS
Emerging non-volatile memory (NVRAM) technologies offer the durability of disk with the byte-addressability of DRAM. These devices will allow software to access persistent data structures directly in NVRAM using processor loads and stores, however, e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5d810ca0829ed43e6ce2f18b4b87f494
https://doi.org/10.1145/2872362.2872381
https://doi.org/10.1145/2872362.2872381
Autor:
Ali G. Saidi, Mark D. Hill, Derek R. Hower, Gabriel Black, Korey Sewell, Somayeh Sardashti, Muhammad Shoaib, Bradford M. Beckmann, Nilay Vaish, Arkaprava Basu, Nathan Binkert, Rathijit Sen, Steven K. Reinhardt, Joel Hestness, Tushar Krishna, Darien Wood
Publikováno v:
ACM SIGARCH Computer Architecture News. 39:1-7
The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b23abd0c2dcc37a9b26b5a4da4cdffe7
https://doi.org/10.1145/2024716.2024718
https://doi.org/10.1145/2024716.2024718
Publikováno v:
ISCA
Many important workloads today, such as web-hosted services, are limited not by processor core performance but by interactions among the cores, the memory system, I/O devices, and the complex software layers that tie these components together. Archit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3eff91186dcc40cb1633a6e95abde69b
https://doi.org/10.1145/1555815.1555800
https://doi.org/10.1145/1555815.1555800
Publikováno v:
ACM Journal on Emerging Technologies in Computing Systems. 4:1-34
This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-efficient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing se
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71107396bc073735e86fce43f5607884
https://doi.org/10.1145/1412587.1412589
https://doi.org/10.1145/1412587.1412589
Autor:
Ali G. Saidi, Geoffrey Blake
Publikováno v:
ISPASS
To function correctly Online, Data-Intensive (OLDI) services require low and consistent service times. Maintaining predictable service times entails requiring 99th or higher percentile latency targets across hundreds to thousands of servers in the da
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fc9184fd0fd2da028dd929237ba5950
https://doi.org/10.1109/ispass.2015.7095781
https://doi.org/10.1109/ispass.2015.7095781
Publikováno v:
ASPLOS
This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kernel-based performance optimization.We believe that this approach is more
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2e1b44dca328242b331872b3a9429cdc
https://doi.org/10.1145/1168917.1168897
https://doi.org/10.1145/1168917.1168897
Autor:
Ali G. Saidi, Ronald G. Dreslinski, Shaun C. D'Souza, Nathan Binkert, Steven K. Reinhardt, Trevor Mudge, Taeho Kgil, Krisztian Flautner
Publikováno v:
ASPLOS
In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::12c6dbacef9b7ccab33df2464635cfb7
https://doi.org/10.1145/1168917.1168873
https://doi.org/10.1145/1168917.1168873
Autor:
Ali G. Saidi, Nathan Binkert, Lisa R. Hsu, Steven K. Reinhardt, Kevin Lim, Ronald G. Dreslinski
Publikováno v:
IEEE Micro. 26:52-60
The M5 simulator is developed specifically to enable research in TCP/IP networking. The M5 simulator provides features necessary for simulating networked hosts, including full-system capability, a detailed I/O subsystem, and the ability to simulate m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d69bc9846d85341a448df1b5d956bb3
https://doi.org/10.1109/mm.2006.82
https://doi.org/10.1109/mm.2006.82
Publikováno v:
MICRO
L1 instruction fetch misses remain a critical performance bottleneck, accounting for up to 40% slowdowns in server applications. Whereas instruction footprints typically fit within last-level caches, they overwhelm L1 caches, whose capacity is limite
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::53ff8b59846a9e1cd35d944d029b7733
https://doi.org/10.1145/2540708.2540731
https://doi.org/10.1145/2540708.2540731