Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Ali Asghar Vatanjou"'
Publikováno v:
Microprocessors and Microsystems. 56:92-100
Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, the functional yield of CMOS logic gates and minimize the leakage energy per cycle in the subthreshold region. In this work, the PMOS/NMOS strength ratio w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a2f104b1a78da7ddaf29df45ccbb52f
https://doi.org/10.1016/j.micpro.2017.11.002
https://doi.org/10.1016/j.micpro.2017.11.002
Publikováno v:
Microprocessors and Microsystems. 48:11-20
Nine D-type Flip-Flop (DFF) architectures were implemented in 28 nm FDSOI at a target, subthreshold, supply voltage of 200 mV. The goal was to identify promising DFFs for ultra low power applications. The single-transistor pass gate DFF, the PowerPC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32af9ffae5f74b671feecaead18e48a1
https://doi.org/10.1016/j.micpro.2016.07.016
https://doi.org/10.1016/j.micpro.2016.07.016
Publikováno v:
IEEE Transactions on Circuits and Systems-II-Express Briefs
—A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e063b5f5e58587770c26e86ef1756b32
https://hdl.handle.net/11250/2591324
https://hdl.handle.net/11250/2591324
Publikováno v:
NORCAS
Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, functional yield of CMOS logic gates in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::762aebb587b5b275e982e1007a80df5d
https://doi.org/10.1109/norchip.2016.7792895
https://doi.org/10.1109/norchip.2016.7792895
Publikováno v:
MIXDES
This paper presents the design of digital logic cells for subthreshold applications using 28 nm ultra-thin body and box fully depleted silicon on insulator technology. The sizing approach relies on balancing pull-up/pull-down networks (PUN/PDN) stren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e5c03df60f6804edcf597cdfd9844c2
https://doi.org/10.1109/mixdes.2016.7529711
https://doi.org/10.1109/mixdes.2016.7529711
Publikováno v:
IEICE Electronics Express. 8:449-453
A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to outpu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34a156033b57d80ca2b24b929748d9a8
https://doi.org/10.1587/elex.8.449
https://doi.org/10.1587/elex.8.449
Publikováno v:
NORCAS
Nine D flip-flop architectures were implemented in 28nm FDSOI at a target, subthreshold, supply voltage of 200mV. The goal was to identify promising D flip-flops for ultra low power applications. The pass gate flip-flop was implemented using 49% of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::783f2b8faaf3dc9fd0e7279d2cf309a4
https://doi.org/10.1109/norchip.2015.7364372
https://doi.org/10.1109/norchip.2015.7364372
Publikováno v:
2015 6th Asia Symposium on Quality Electronic Design (ASQED).
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“V dd ”) down to 84 mV. The low V dd might be the lowest reported for comparable CMOS circuitry, not dependi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::281b500e928c2b87c82af66e12ff6abc
https://doi.org/10.1109/acqed.2015.7273999
https://doi.org/10.1109/acqed.2015.7273999
Publikováno v:
ECCTD
When using standard multi-V t CMOS processes when making logic gates, often for example Low-V t (LVT), or Standard-V t (SVT) or High-V t (HVT) transistors are used within one and the same basic logic building block, like for example a NAND or NOR cir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86b10d33a8642fb4e767a162ab647a88
https://doi.org/10.1109/ecctd.2015.7300053
https://doi.org/10.1109/ecctd.2015.7300053
Publikováno v:
ECCTD
Four different flip-flops dimensioned for subthresh-old operation have been designed and implemented in layouts. The four full custom, race-free, D-flip-flops were implemented in a standard 65 nm CMOS process and verified by measurements, when used i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::466e9da1d961cb99379fa025895f4d67
https://doi.org/10.1109/ecctd.2015.7300058
https://doi.org/10.1109/ecctd.2015.7300058