Zobrazeno 1 - 10
of 152
pro vyhledávání: '"Alexis Farcy"'
Autor:
Guillaume Moritz, Gael Pillonnet, Frédéric Berger, Denis Dutoit, Alexandre Arriordaz, David Coriat, Lucile Arnaud, Julian Pontes, Eric Guthmuller, Christian Bernard, Fabien Clermidy, Alexis Farcy, Didier Varreau, P. Coudrain, Alain Greiner, J. Durupt, Michel Harrand, Didier Lattard, Quentin L. Meunier, Jean Charbonnier, Ivan Miro-Panades, Sebastien Thuries, Cesar Fuguet, Arnaud Garnier, Severine Cheramy, Alain Gueugnot, Pascal Vivet, Yvain Thonnart
Publikováno v:
IEEE Journal of Solid-State Circuits
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d4012e9cdfa24d7a486fffa94ba46e77
https://hal.archives-ouvertes.fr/hal-03072959/document
https://hal.archives-ouvertes.fr/hal-03072959/document
Autor:
Frederic Boeuf, Jean Charbonnier, Benoit Charbonnier, Stephane Bernabe, F. Ponthenier, Pierre Tissier, Alexis Farcy, Jean-Emmanuel Broquin, Remi Velard
Publikováno v:
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).
In the framework of High Performance Computing and Datacom, silicon photonics interposers propose an interesting approach, while providing new challenges. This paper demonstrates such an integration and focuses on TSV Mid integration impact on sensit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c460e695111e870cb95c439ca01ed95
https://doi.org/10.1109/estc48849.2020.9229858
https://doi.org/10.1109/estc48849.2020.9229858
Autor:
Lucile Arnaud, David Coriat, Cesar Fuguet, Perceval Coudrain, Julian Pontes, Ivan Miro-Panades, Sebastien Thuries, J. Durupt, Didier Varreau, D. Lattard, Alexis Farcy, Alexandre Arriordaz, Eric Guthmuller, Alain Greiner, Christian Bernard, Severine Cheramy, Gael Pillonnet, Guillaume Moritz, Alain Gueugnot, Yvain Thonnart, Quentin L. Meunier, Frédéric Berger, Jean Charbonnier, Pascal Vivet, Fabien Clermidy, Michel Harrand, Arnaud Garnier, Denis Dutoit
Publikováno v:
ISSCC
In the context of high-performance computing and big-data applications, the quest for performance requires modular, scalable, energy-efficient, low-cost manycore systems. Partitioning the system into multiple chiplets 3D-stacked onto large-scale inte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::290cb64ff9abb64db868f6d26d6fcd40
https://doi.org/10.1109/isscc19947.2020.9062927
https://doi.org/10.1109/isscc19947.2020.9062927
Autor:
Yann Lamy, Anne-Laure Perrier, Khadim Dieng, Olivier Guiller, Bernard Flechet, Alexis Farcy, Philippe Artillan, Cedric Bermond, Thierry Lacrevaz, Grégory Houzet, Sylvain Joblot
Publikováno v:
IEEE Transactions on Components Packaging and Manufacturing Technology Part B
IEEE Transactions on Components Packaging and Manufacturing Technology Part B, 2017, 7 (4), pp.477-484. ⟨10.1109/TCPMT.2017.2655939⟩
IEEE Transactions on Components Packaging and Manufacturing Technology Part B, Institute of Electrical and Electronics Engineers (IEEE), 2017, 7 (4), pp.477-484. ⟨10.1109/TCPMT.2017.2655939⟩
IEEE Transactions on Components Packaging and Manufacturing Technology Part B, 2017, 7 (4), pp.477-484. ⟨10.1109/TCPMT.2017.2655939⟩
IEEE Transactions on Components Packaging and Manufacturing Technology Part B, Institute of Electrical and Electronics Engineers (IEEE), 2017, 7 (4), pp.477-484. ⟨10.1109/TCPMT.2017.2655939⟩
International audience; The feasibility of cointegration of new capacitors, named “through silicon capacitors” (TSCs) with “through silicon vias” in silicon interposers has recently been demonstrated. Two architectures of TSC are extensively
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::47bc48de94b0dad144236ff674e0a8cf
https://doi.org/10.1109/tcpmt.2017.2655939
https://doi.org/10.1109/tcpmt.2017.2655939
Autor:
Didier Campos, P. Coudrain, Yorrick Exbrayat, Lucile Arnaud, Stephane Minoret, F. Ponthenier, Andrea Vinci, Severine Cheramy, Alain Gueugnot, Daniel Scevola, Cesar Fuguet Tortolero, P. Chausse, Roselyne Segaud, Giovanni Romano, Christophe Aumont, Didier Lattard, Jean Charbonnier, Pierre-Emile Philip, C. Ribiere, Arnaud Garnier, Jean Michailos, Mathilde Gottardi, Raphael Eleouet, Frédéric Berger, Eric Guthmuller, Gilles Simon, Jerome Beltritti, Gilles Romero, Maxime Argoud, Denis Dutoit, Alexis Farcy, Nacima Allouti, Therry Mourier, Remi Velard, Pascal Vivet, Corinne Legalland
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interco
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8afe955b96b263c988971d8f1f91372
https://doi.org/10.1109/ectc.2019.00092
https://doi.org/10.1109/ectc.2019.00092
Autor:
Yann Henrion, Severine Cheramy, Halim Bilgen, Joris Jourdon, Alexis Farcy, Pascal Vivet, Didier Lattard, Edith Beigne, Lucile Arnaud, E. Deloffre, Imed Jani
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
Cu/oxide Hybrid Bonding (HB) technology is currently the ultimate fine pitch 3D interconnect solution to reach submicron pitches. It's an attractive technique to address the needs of several applications such as smart imagers, high-performance comput
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3229ea2543acf6bb592faa0e3580973
https://doi.org/10.1109/ectc.2019.00272
https://doi.org/10.1109/ectc.2019.00272
Autor:
Papa Momar Souare, Laurent Le Pailleur, Denis Dutoit, Francois de Crecy, Cristiano Santos, Pascal Vivet, Sylvain Dumas, Vincent Fiori, Didier Lattard, Haykel Ben-Jamaa, Perceval Coudrain, Severine Cheramy, R. Prieto, Christian Chancel, Jean-Philippe Colonna, Alexis Farcy
Publikováno v:
IEEE Design & Test. 33:21-36
This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7755d96506c4f50ac23aa638214fb401
https://doi.org/10.1109/mdat.2015.2506678
https://doi.org/10.1109/mdat.2015.2506678
Publikováno v:
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2018, 18 (4), pp.529-533. ⟨10.1109/TDMR.2018.2881418⟩
IEEE Transactions on Device and Materials Reliability, 2018, 18 (4), pp.529-533. ⟨10.1109/TDMR.2018.2881418⟩
IEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2018, 18 (4), pp.529-533. ⟨10.1109/TDMR.2018.2881418⟩
IEEE Transactions on Device and Materials Reliability, 2018, 18 (4), pp.529-533. ⟨10.1109/TDMR.2018.2881418⟩
In 3-D integration, dice are vertically interconnected with through silicon via (TSV), which consist of holes etched in a thinned silicon substrate and filled with copper. This process induces thermal strain in surrounding silicon. New trends in 3-D
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ced909fa10606ef1e31bf297998ab582
https://hal.archives-ouvertes.fr/hal-02114463
https://hal.archives-ouvertes.fr/hal-02114463
Autor:
Thierry Lacrevaz, Jean-Charles Barbe, Remi Velard, Alexis Farcy, Lucile Cheramy, Kevin Morot, Bernard Flechet, Roselyne Segaud, Helene Jacquinot, Lucile Arnaud
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. pp.2000-2006, ⟨10.1109/ECTC.2018.00300⟩
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. pp.2000-2006, ⟨10.1109/ECTC.2018.00300⟩
This work aims at providing a RLCG modeling and performance optimization of Redistribution Layer (RDL) in a non-HR substrate up to 67 GHz. Similarly to TSVs, RDL modeling can not be assessed by standard parasitic extraction CAD tools. Therefore, we p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2e4971ab4228f2193472a951f2cd5b07
https://hal.science/hal-02015694
https://hal.science/hal-02015694
Autor:
Simon Gousseau, Frank Fournel, Joris Jourdon, N. Bresson, V. Balan, M. Arnoux, Lucile Arnaud, C. Euvrard, Alexis Farcy, Sandrine Lhostis, S. Guillaumet, Y. Exbrayat, Stephane Moreau, Didier Lattard, Imed Jani, E. Deloffre, A. Jouve
Publikováno v:
IRPS
This paper presents the description of direct hybrid bonding technology for the fabrication of vertical interconnects thanks to wafer-to-wafer bonding. Process robustness is analyzed through morphological and electrical results. The electrical charac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1233924cac7498777fc45672c9a42b3
https://doi.org/10.1109/irps.2018.8353591
https://doi.org/10.1109/irps.2018.8353591