Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Alexey S. Filippov"'
Publikováno v:
Proceedings of the XXth Conference of Open Innovations Association FRUCT, Vol 664, Iss 18, Pp 9-14 (2016)
The driving forces for this project are demands for a hardware, reconfigurable, high performance, low cost and low power solution that could be used in a widest range of Internet of Things (IoT) devices. The solution should be able to secure computer
Externí odkaz:
https://doaj.org/article/97fc1b99041e4aa994d68b756cfaf7dc
Publikováno v:
Proceedings of the XXth Conference of Open Innovations Association FRUCT, Vol 26, Iss 1, Pp 23-29 (2020)
FRUCT
FRUCT
The article is devoted to a research of an effectiveness of high-level synthesis approach, based on Xilinx's high-level synthesis tool - Vivado, for a hardware implementation of sorting algorithms, which are one of the key algorithm for Big Data anal
Publikováno v:
Communications in Computer and Information Science ISBN: 9783030646158
RuSCDays
RuSCDays
The article describes results of our research of hardware implementation efficiency of sorting algorithms created by using of Xilinx’s High-Level Synthesis tools, the Vivado HLS package, and FPGAs. The term efficiency, used in the research, defined
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c50e27238984634e76508ed68d2f393
https://doi.org/10.1007/978-3-030-64616-5_39
https://doi.org/10.1007/978-3-030-64616-5_39
Publikováno v:
Proceedings of the XXth Conference of Open Innovations Association FRUCT, Vol 388, Iss 17, Pp 116-121 (2015)
FRUCT
FRUCT
Design of command and data handling subsystems for small satellites is in the focus for many in space industry and academia. For today a plenty of small satellites have been designed, manufactured and launched. However, while the application calls fo
Publikováno v:
2017 IEEE 37th International Conference on Electronics and Nanotechnology (ELNANO).
For critical aerospace applications that experience a high intensity of single event upsets, the cache of a processor has to be protected against soft errors. This poses a challenge for cache design, since implemented redundancy causes timing and per