Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Alexandre Joannou"'
Autor:
Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno Van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore
Publikováno v:
IEEE Design & Test. :1-1
TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a human-readable specification that can also
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1c3df44ab2b72d1129702ce1b1f60b20
https://doi.org/10.1109/mdat.2023.3262741
https://doi.org/10.1109/mdat.2023.3262741
Autor:
Peter Sewell, Khilan Gudka, David Chisnall, Alexander Richardson, Robert N. M. Watson, Alexandre Joannou, Stacey Son, John Baldwin, Edward Napierala, Michael Roe, Robert M. Norton, Nathaniel Wesley Filardo, Alfredo Mazzinghi, Simon W. Moore, Jessica Clarke, Jonathan Woodruff, Sam Ainsworth, Brooks Davis, Brett F. Gutstein, Peter G. Neumann, Lucian Paul-Trifu, A. Theodore Markettos, Hongyan Xia, Timothy M. Jones
Publikováno v:
Proceedings of the 41st IEEE Symposium on Security and Privacy (SP)
2020 IEEE Symposium on Security and Privacy (SP)
IEEE Symposium on Security and Privacy
2020 IEEE Symposium on Security and Privacy (SP)
IEEE Symposium on Security and Privacy
Use-after-free violations of temporal memory safety continue to plague software systems, underpinning many high-impact exploits. The CHERI capability system shows great promise in achieving C and C++ language spatial memory safety, preventing out-of-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::aca2234b627b684664fc034652d5b50c
Autor:
Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, Graeme Barnes, David Chisnall, Jessica Clarke, Brooks Davis, Lee Eisen, Nathaniel Wesley Filardo, Richard Grisenthwaite, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alexander Richardson, Peter Rugg, Peter Sewell, Stacey Son, Hongyan Xia
This technical report describes CHERI ISAv8, the eighth version of the CHERI architecture being developed by SRI International and the University of Cambridge. This design captures ten years of research, development, experimentation, refinement, form
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f5b2e44e3ab9cca15f234ee537f453d
Autor:
Robert N. M. Watson, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore, Peter Sewell, Arm Limited
The CHERI protection model extends contemporary Instruction Set Architectures (ISAs) with support for architectural capabilities. The UKRI Digital Security by Design (DSbD) programme is supporting the creation of Arm’s prototype Morello processor,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5771d115e08f91034b30770cbef44133
Autor:
Michael Roe, Simon W. Moore, Alexandre Joannou, Khilan Gudka, Peter G. Neumann, Jonathan Woodruff, Robert Norton, J. Edward Maste, Stacey Son, A. Theodore Markettos, Ben Laurie, Robert N. M. Watson, Brooks Davis, David Brazdil, David Chisnall
Publikováno v:
ASPLOS
Java provides security and robustness by building a high- level security model atop the foundation of memory protection. Unfortunately, any native code linked into a Java program – including the million lines used to implement the standard library
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::45826b388701e9ab0d83cd07e7650eab
https://doi.org/10.1145/3093315.3037725
https://doi.org/10.1145/3093315.3037725
Autor:
Matthew Naylor, Michael Roe, Thomas Bauereiss, Brian Campbell, Kyndylan Nienhuis, Simon W. Moore, Ian Stark, Peter Sewell, Robert M. Norton, Peter G. Neumann, Alexandre Joannou, Robert N. M. Watson, Anthony Fox
Publikováno v:
Nienhuis, K, Joannou, A, Bauereiss, T, Fox, A, Roe, M, Campbell, B, Naylor, M, Norton, R M, Moore, S W, Neumann, P G, Stark, I, Watson, R N M & Sewell, P 2020, Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process . in 2020 IEEE Symposium on Security and Privacy (SP) . Institute of Electrical and Electronics Engineers (IEEE), San Francisco, CA, USA, pp. 1003-1020, 41st IEEE Symposium on Security and Privacy, San Francisco, California, United States, 18/05/20 . https://doi.org/10.1109/SP40000.2020.00055
2020 IEEE Symposium on Security and Privacy (SP)
Proceedings of the 41st IEEE Symposium on Security and Privacy (SP)
IEEE Symposium on Security and Privacy
2020 IEEE Symposium on Security and Privacy (SP)
Proceedings of the 41st IEEE Symposium on Security and Privacy (SP)
IEEE Symposium on Security and Privacy
The root causes of many security vulnerabilities include a pernicious combination of two problems, often regarded as inescapable aspects of computing. First, the protection mechanisms provided by the mainstream processor architecture and C/C++ langua
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::088194b0b16081fc68eabf7d11140121
Autor:
Alexandre Joannou, Khilan Gudka, Peter G. Neumann, David Chisnall, Robert M. Norton, A. Theodore Markettos, Jonathan Woodruff, Simon W. Moore, Nathaniel Wesley Filardo, Brooks Davis, Michael Roe, Robert N. M. Watson, Anthony Fox, Hongyan Xia
We present CHERI Concentrate, a new fat-pointer compression scheme applied to CHERI, the most developed capability-pointer system at present. Capability fat pointers are a primary candidate to enforce fine-grained and non-bypassable security properti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d0e95515760db766c3e26d5ad557891a
https://www.repository.cam.ac.uk/handle/1810/292406
https://www.repository.cam.ac.uk/handle/1810/292406
Autor:
Robert N. M. Watson, Brooks Davis, Peter Sewell, Alexandre Joannou, Alfredo Mazzinghi, Nathaniel Wesley Filardo, Jonathan Woodruff, Alexander Richardson, Khilan Gudka, Jessica Clarke, Robert M. Norton, Ben Laurie, Stacey Son, David Chisnall, Simon W. Moore, Michael Roe, Peter G. Neumann, John Baldwin, Edward Napierala, J. Edward Maste, A. Theodore Markettos
Publikováno v:
ASPLOS
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
The CHERI architecture allows pointers to be implemented as capabilities (rather than integer virtual addresses) in a manner that is compatible with, and strengthens, the semantics of the C language. In addition to the spatial protections offered by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f1e757dbf0968dafc0479d4c9f8a8c46
Autor:
Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, Hongyan Xia
This technical report describes CHERI ISAv7, the seventh version of the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being developed by SRI International and the University of Cambridge. This design captur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5e58ff1ab5227b612ba7ee3a0b087fd
Autor:
Jonathan Anderson, Peter G. Neumann, Robert Norton, Stacey Son, Brooks Davis, Jonathan Woodruff, Alexandre Joannou, Nirav H. Dave, Khilan Gudka, Ed Maste, Steven J. Murdoch, A. Theodore Markettos, Michael Roe, Simon W. Moore, Colin Rothwell, Munraj Vadera, Ben Laurie, Robert N. M. Watson, David Chisnall
Publikováno v:
IEEE Micro. 36:38-49
Capability Hardware Enhanced RISC Instructions (CHERI) supplement the conventional memory management unit (MMU) with instruction-set architecture (ISA) extensions that implement a capability system model in the address space. CHERI can also underpin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2ae4b85c6e4842aeeda73fa15322bae7
https://doi.org/10.1109/mm.2016.84
https://doi.org/10.1109/mm.2016.84