Zobrazeno 1 - 9 of 9 pro vyhledávání: '"Alexandre Dray"'
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Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology
Autor: Ghislain Troussier, Johan Bourgeat, Nicolas Guitard, D. Marin-Cudraz, Jean Jimenez, Alexandre Dray, Philippe Galy, Blaise Jacquier
Publikováno v: Microelectronics Reliability. 52:1998-2004
The purpose of this paper is to present a new trigger design solution to address a double challenge. The first challenge is to trigger a dual back to back SCR during an ESD event with symmetrical response. And the second one is to obtain a pull-up fu
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cfc73c4af385c7c1006f95f2561e068b
https://doi.org/10.1016/j.microrel.2012.06.117
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4
Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS–BICMOS technologies
Autor: J. Beltritti, Philippe Galy, M. Bilinski, R. Chevallier, Sylvain Dudit, V. Varo, Frank Jezequel, C. Boutonnat, Ph. Larre, E. Petit, Michel Vallet, Jean Jimenez, Alexandre Dray
Publikováno v: Microelectronics Reliability. 50:1388-1392
The main purpose of this paper is to present typical silicon signatures induced by charged device stress and to discuss the nature of failures. This first inventory is elaborated on advanced CMOS–BICMOS technologies until C32 nm dual oxide. It is w
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b9d27ebad3f1758ee058aebc4f1b9edb
https://doi.org/10.1016/j.microrel.2010.07.137
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5
EOS characterization methodology applied to disable feature of ESD power clamps
Autor: Vicky Batra, Luong Viet Phung, Bruno Allard, Divya Agarwal, Nicolas Guitard, Alexandre Dray, Jorge Loayza, Blaise Jacquier
Publikováno v: 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
This work presents an EOS characterization methodology for ESD clamps. BigFET-based and SCR-based power clamps with and without disable feature are characterized. Thanks to the proposed characterization methodology, robustness comparison is provided
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::aaebb81d5cf60c34e94bf4f5102b8484
https://doi.org/10.1109/eosesd.2015.7314782
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6
Characterization and Modeling of Gate-Induced-Drain-Leakage
Autor: R. Bouchakour, Alexandre Dray, Pascal Masson, M. Minondo, Andre Juge, Fabien Gilibert, Francois Agut, Denis Rideau
Publikováno v: IEICE Transactions on Electronics. :829-837
We present measurements of Gate-Induced-Drain-Leakage at various temperatures and terminal biases. Besides Band-to-Band tunneling leakage observed at high Drain-to-Gate voltage v DG , we also observed Trap-Assisted-Tunneling leakage current at lower
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4c8ff1c8596397e4f643e0955d9dd1b8
https://doi.org/10.1093/ietele/e88-c.5.829
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7
BIMOS transistor and its applications in ESD protection in advanced CMOS technology
Autor: Ph. Galy, Ghislain Troussier, D. Marin-Cudraz, Johan Bourgeat, Nicolas Guitard, Boris Heitz, Jean Jimenez, Alexandre Dray, H. Beckrich-Ros
Publikováno v: ICICDT
BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c61d5d8bdcc9937e78eb59f74c341945
https://doi.org/10.1109/icicdt.2012.6232878
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8
Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology
Autor: Ph. Galy, Johan Bourgeat, Jean Jimenez, Alexandre Dray, Christophe Entringer, Blaise Jacquier
Publikováno v: 2010 IEEE International Conference on Integrated Circuit Design and Technology.
The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD pro
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::95a59365857d5d815cc192513d00dd41
https://doi.org/10.1109/icicdt.2010.5510292
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9
Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET]
Autor: Alexandre Dray, Andre Juge, Fabien Gilibert, M. Minondo, Gilles Gouget, Francois Agut, L. Giguerre, Denis Rideau
Publikováno v: Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).
We present measurements of GIDL at various temperatures and terminal biases. Besides band-to-band (BBT) tunneling leakage observed at high drain-to-gate voltage V/sub DG/, we also observed trap-assisted-tunneling (TAT) leakage currents at lower V/sub
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8cf2de624b25c0334f29e2031bb5d5cc
https://doi.org/10.1109/icmts.2004.1309469
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