Zobrazeno 1 - 10
of 32
pro vyhledávání: '"Alexander Taubin"'
Publikováno v:
The International Journal of Advanced Manufacturing Technology. 14:750-759
Unfoldings of Petri nets (PN) provide a method for the analysis of concurrent systems without restoring the state space of a system. This allows one to overcome the “state explosion” problem. Many properties of the initial PN (boundedness, safety
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::377a2ed875f3175be0f11de994785bb3
https://doi.org/10.1007/bf01438227
https://doi.org/10.1007/bf01438227
Publikováno v:
Formal Methods in System Design. 12:5-38
This paper suggests a way for Petri Net analysis by checking the ordering relations between places and transitions. The method is based on unfolding the original net into an equivalent acyclic description. We improved on the previously known cutoff c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3de784c1dd7ab16070dbbc9da954a446
https://doi.org/10.1023/a:1008669013857
https://doi.org/10.1023/a:1008669013857
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17:1184-1199
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. Previous work has shown that full-scan delay-fault testing of asynchronous circuits is feasible. In this work, we tackle
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f77ab6b62d74831bc0ddaf17496f4fd
https://doi.org/10.1109/43.736191
https://doi.org/10.1109/43.736191
Autor:
Alexander Taubin, Mark G. Karpovsky
Publikováno v:
IEEE Transactions on Information Theory. 50:1818-1820
A code C detects error e with probability 1-Q(e),ifQ(e) is a fraction of codewords y such that y, y+e/spl isin/C. We present a class of optimal nonlinear q-ary systematic (n, q/sup k/)-codes (robust codes) minimizing over all (n, q/sup k/)-codes the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::822a9b90f070257cad8bc4f24f5e3787
https://doi.org/10.1109/tit.2004.831844
https://doi.org/10.1109/tit.2004.831844
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 7:117-135
The problems of self-timed behavior specification and verification are considered on the basis of an event model--Change Diagram (CD). The descriptive power of a CD model is demonstrated by comparing the CD with Signal Transition Graphs (STG). CD dif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c26e78be6a0aa55d32c59311d4ec90d
https://doi.org/10.1007/bf02108193
https://doi.org/10.1007/bf02108193
Publikováno v:
Formal Methods in System Design. 4:33-75
The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a8e0617bb313f0275288ad6ed0518df
https://doi.org/10.1007/bf01383956
https://doi.org/10.1007/bf01383956
Autor:
Alexander Taubin, Alexander V. Smirnov
Publikováno v:
ASYNC
We present a heuristic based approach towards analyzing and optimizing the throughput of asynchronous pipelined circuits. Optimization allows specification of the target throughput. A variety of handshaking protocols and implementations are supported
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9adceb78ca8fc892338cfd45f5ac075e
https://doi.org/10.1109/async.2009.31
https://doi.org/10.1109/async.2009.31
Publikováno v:
DATE
Cryptographic hardware is vulnerable to power analysis attacks. To resist these attacks, special balanced dual-rail gates have been developed which have equal power consumption for all valid data values and transitions. A limitation of existing desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d9bc2f14154ac831282c22d7ec72cad9
https://doi.org/10.1145/1403375.1403685
https://doi.org/10.1145/1403375.1403685
Publikováno v:
ACSD
Register transfer level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking technology and progressive increase in clock frequency are bringing cloc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c78a53311ac9580f0541be95e980c60
https://doi.org/10.1109/acsd.2005.3
https://doi.org/10.1109/acsd.2005.3
Autor:
Alexander Taubin, Tejpal Singh
Publikováno v:
2006 49th IEEE International Midwest Symposium on Circuits and Systems.
This paper presents a new low latency Crossbar design that can be used to interface systems working at different frequencies. For case of multiple input ports contending for same output port contemporary designs provide localized arbitration solution
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d469a8d405a5e24449520d1906123d38
https://doi.org/10.1109/mwscas.2006.382003
https://doi.org/10.1109/mwscas.2006.382003