Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Alexander L. Barr"'
Fabrication and operation of sub-50 nm strained-Si on Si/sub 1-x/Ge/sub x/ Insulator (SGOI) CMOSFETs
Autor:
X.-D. Wang, S. Parsons, Mike Kottke, D. Tekleab, Aaron Thean, Bich-Yen Nguyen, P. Beckage, Mariam Sadaka, J. Mogab, S. Kalpat, C. Mazure, Ted R. White, Dharmesh Jawarani, Qianghua Xie, M. Zavala, T. Nguyen, M. Canonico, Ran Liu, Stefan Zollner, D. Eades, Rode R. Mora, Alexander L. Barr
Publikováno v:
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
First functional 45 nm SGOI CMOS devices on bonded SGOI substrates with T/sub SOI/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::693d1a5782f342847888be6c71d8a07c
https://doi.org/10.1109/soi.2004.1391620
https://doi.org/10.1109/soi.2004.1391620
Autor:
A. Vandooren, Ted R. White, Raj Rai, M. Zalava, Aaron Thean, R. Noble, B. Xie, L. Prabhu, Yang Du, Veer Dhandapani, S. Kalpat, Alexander L. Barr, X.-D. Wang, Da Zhang, Michael A. Sadd, Mariam Sadaka, James K. Schaeffer, T. Nguyen, M. Ramon, Marius K. Orlowski, J. Mogab, Vidya Kaushik, S. Samavedam, D. Eades, Brian J. Goolsby, Michael A. Mendicino, Thuy B. Dao, Zhonghai Shi, Dina H. Triyoso, Ran Liu, Stefan Zollner, T. Stephen, Philip J. Tobin, Leo Mathew, Victor H. Vartanian, S. Venkatesan, Bich-Yen Nguyen, J. Jiang, Shawn G. Thomas
Publikováno v:
Scopus-Elsevier
In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::19c75e058af9a0cb895bb4daa8962a36
https://doi.org/10.1109/icicdt.2004.1309953
https://doi.org/10.1109/icicdt.2004.1309953
Autor:
D. Roan, Marius K. Orlowski, Daniel T. Pham, M. Zavala, Alexander L. Barr, K. Sphabmixay, R. Rai, A. Duvallet, Bich-Yen Nguyen, A. Vandooren, J. Schaeffer, S. Samavedam, M. Huang, Leo Mathew, Tab A. Stephens, Bruce E. White, J. Hughes, Yang Du, Marc A. Rossow, J. Mogab, Dina H. Triyoso, Aaron Thean, S. Egley, I. To, Thuy B. Dao, Ted R. White
Publikováno v:
IEEE International Electron Devices Meeting 2003.
We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continue
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::757374a79686d4b35ff78e9441c54811
https://doi.org/10.1109/iedm.2003.1269441
https://doi.org/10.1109/iedm.2003.1269441