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Lattice-based cryptography (LBC) performs polynomial multiplication using the Number Theoretic Transform (NTT), in order to reduce the polynomial multiplication complexity from O(n 2 ) to O(n log n). Although NTT-based multipliers offer the fastest w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e25b54c9a7e8d57c6ff86a4e2d18924b
https://zenodo.org/record/7413465
https://zenodo.org/record/7413465
Autor:
Evangelos Haleplidis, Apostolos P. Fournaris, Vassilis Paliouras, Thanasis Tsakoulis, Alexander El-Kady
Publikováno v:
2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)
VLSI-SoC
29th IFIP/IEEE International Conference on Very Large Scale Integration
VLSI-SoC
29th IFIP/IEEE International Conference on Very Large Scale Integration
Lattice-based cryptography performs polynomial multiplication using the Number Theoretic Transform (NTT), in order to reduce the polynomial multiplication complexity fromO(n2)toO(nlogn). NTT has been in the center of investigation in cryptography spa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7b7a0da865c843f06bc95b82dd57bb04
https://zenodo.org/record/5727083
https://zenodo.org/record/5727083
Autor:
Apostolos P. Fournaris, Alexander El-Kady, Charis Dimopoulos, Thanasis Tsakoulis, Evangelos Haleplidis, Odysseas Koufopavlou
Publikováno v:
DSD
2021 24th Euromicro Conference on Digital System Design (DSD)
2021 24th Euromicro Conference on Digital System Design (DSD)
Lattice based cryptography can be considered a candidate alternative for post-quantum cryptosystems offering key exchange, digital signature and encryption functionality. Number Theoretic Transform (NTT) can be utilized to achieve better performance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6bc808279b0ceceb003e1a8015183594
https://zenodo.org/record/5702344
https://zenodo.org/record/5702344
Publikováno v:
2019 Panhellenic Conference on Electronics & Telecommunications (PACET).
An architecture enabling a flexible on-board simulation and verification method for complex user-specific IPs is presented. The proposed method relies on an FPGA-SoC implementation of a golden simulation and verification model, properly optimized for