Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Alex Solomatnikov"'
Publikováno v:
ASPLOS
Programming language and operating system support for efficient concurrency-safe access to shared data is a key concern for the effective use of multi-core processors. Most research has focused on the software model of multiple threads accessing this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7510a2c5d0057811df510bfd3fd5e999
https://doi.org/10.1145/2248487.2151007
https://doi.org/10.1145/2248487.2151007
Autor:
Megan Wachs, Mark Horowitz, Benjamin C. Lee, Christos Kozyrakis, Wajahat Qadeer, Alex Solomatnikov, Omid Azizi, Rehan Hameed, Stephen Richardson
Publikováno v:
Communications of the ACM. 54:85-93
Scaling the performance of a power limited processor requires decreasing the energy expended per instruction executed, since energy/op * op/second is power. To better understand what improvement in processor efficiency is possible, and what must be d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ba63919997fbaf2d7d50a2349e24fae
https://doi.org/10.1145/2001269.2001291
https://doi.org/10.1145/2001269.2001291
Autor:
Omid Azizi, Mark Horowitz, Megan Wachs, Ofer Shacham, Kyle Kelley, John P. Stevenson, Zain Asgar, Wajahat Qadeer, Benjamin C. Lee, Stephen Richardson, Alex Solomatnikov, Amin Firoozshahian
Publikováno v:
IEEE Micro. 30:9-24
Because of technology scaling, power dissipation is today's major performance limiter. Moreover, the traditional way to achieve power efficiency, application-specific designs, is prohibitively expensive. These power and cost issues necessitate rethin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99fcf7cdbcc343c145045f5bfd7befc2
https://doi.org/10.1109/mm.2010.81
https://doi.org/10.1109/mm.2010.81
Autor:
Amin Firoozshahian, Alex Solomatnikov, Hideho Arakida, Christos Kozyrakis, Mark Horowitz, Jacob Leverich
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 5:1-30
There are two competing models for the on-chip memory in Chip Multiprocessor (CMP) systems: hardware-managed coherent caches and software-managed streaming memory . This paper performs a direct comparison of the two models under the same set of assum
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be6aca3b111df9370e1131bc782918b3
https://doi.org/10.1145/1455650.1455651
https://doi.org/10.1145/1455650.1455651
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10:469-476
In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low volt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a386e7867fbc142b141c244b213a46b5
https://doi.org/10.1109/tvlsi.2002.800519
https://doi.org/10.1109/tvlsi.2002.800519
Publikováno v:
ICS
Sparse matrix-vector multiply (SpMV) is a critical task in the inner loop of modern iterative linear system solvers and exhibits very little data reuse. This low reuse means that its performance is bounded by main-memory bandwidth. Moreover, the rand
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb1e93cef66301ca92f9413af52d2f4a
https://doi.org/10.1145/2304576.2304603
https://doi.org/10.1145/2304576.2304603
Autor:
Rehan Hameed, Stephen Richardson, Alex Solomatnikov, Wajahat Qadeer, Mark Horowitz, Omid Azizi, Benjamin C. Lee, Christos Kozyrakis, Megan Wachs
Publikováno v:
ISCA
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance and energy efficiency. This paper explores the sources of these performa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5c69d3dcf8b139f795b5edcc2d1ef80
https://doi.org/10.1145/1815961.1815968
https://doi.org/10.1145/1815961.1815968
Autor:
Mark Horowitz, Alex Solomatnikov, Stephen Richardson, Megan Wachs, Zain Asgar, Wajahat Qadeer, Amin Firoozshahian, Ofer Shacham
Publikováno v:
MICRO
Building hardware prototypes for computer architecture research is challenging. Unfortunately, development of the required software tools (compilers, debuggers, runtime) is even more challenging, which means these systems rarely run real applications
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e4cfc83ee83217c4de92e4528fa584a
https://doi.org/10.1145/1669112.1669159
https://doi.org/10.1145/1669112.1669159
Autor:
Amin Firoozshahian, Ofer Shacham, Alex Solomatnikov, Mark Horowitz, Stephen Richardson, Zain Asgar, Christos Kozyrakis
Publikováno v:
ISCA
As CPU cores become building blocks, we see a great expansion in the types of on-chip memory systems proposed for CMPs. Unfortunately, designing the cache and protocol controllers to support these memory systems is complex, and their concurrency and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8018e5b4039783e5ceed845e612d7f1
https://doi.org/10.1145/1555754.1555805
https://doi.org/10.1145/1555754.1555805
Autor:
Megan Wachs, Mark Horowitz, Stephen Richardson, Amin Firoozshahian, Ofer Shacham, Alex Solomatnikov
Publikováno v:
MICRO
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a hi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fba3c0f209b13206fa60c7e76a5a1af1
https://doi.org/10.1109/micro.2008.4771799
https://doi.org/10.1109/micro.2008.4771799