Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Alessandro Strano"'
Publikováno v:
ACM Transactions on Embedded Computing Systems
At the core of an efficient chip multiprocessors (CMP) is support for unicast and multicast routing, low implementation costs, and the ability to isolate concurrent applications with maximum utilization of the CMP. We present an efficient logic-based
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::81e2ebb8afaae1e45cc6b7a1590a209b
https://doi.org/10.1145/2485984.2485995
https://doi.org/10.1145/2485984.2485995
Publikováno v:
Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip.
The digital design convergence, together with the new usage models of mobile devices, are raising the clear need for new requirements such as flexible partitioning, runtime adaptivity, reliability. In turn, such feature-rich architectures make the te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64901d0156ed77f2d5f4b8c8e81f283e
https://doi.org/10.1145/2556857.2556859
https://doi.org/10.1145/2556857.2556859
In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network op
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d47229649f5f22df2a7fcb675e1b9117
https://doi.org/10.4018/978-1-4666-6034-2.ch016
https://doi.org/10.4018/978-1-4666-6034-2.ch016
Autor:
Eckhard Grass, Christoph Heer, Milos Krstic, Alessandro Strano, Mohammad Reza Kakoee, Davide Bertozzi, Birgit Sanders, Gabriele Miorandi, Alberto Ghiribaldi, Luca Benini, Xin Fan
The GALS methodology has been discussed for many years, but only a few relevant implementations in silicon have been done. This chapter describes the implementation and test of the Moonrake Chip – a complex GALS demonstrator implemented in 40 nm CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ece86dfc34c0a0ff54aa2d0d3905932e
https://doi.org/10.4018/978-1-4666-6034-2.ch017
https://doi.org/10.4018/978-1-4666-6034-2.ch017
Publikováno v:
IET Computers & Digital Techniques
Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3b25bbe028000ae64f62732758cbe6a4
http://hdl.handle.net/11392/1733898
http://hdl.handle.net/11392/1733898
Autor:
Michele Favalli, Jose Flich, Davide Bertozzi, Alessandro Strano, Francisco Triviño, José L. Sánchez, Daniele Ludovici, Alberto Ghiribaldi, Francisco J. Alfaro
Publikováno v:
ACM Transactions on Embedded Computing Systems
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
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[EN] Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. One one hand, a fast and scalable built-in self-testing and self-diagn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::35a803dd1cbfe80c3bb662907ba81b3a
Autor:
Frank Olaf Sem-Jacobsen, Tor Skeie, F. Gilabert, Samuel Rodrigo, Alessandro Strano, Davide Bertozzi
Publikováno v:
ACM Transactions on Embedded Computing Systems
Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-awareness is a new challenge present in NoCs that must be efficiently handled by the routing functionality as it introduces irregularities in the commonly used 2-D me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::30d52c193127e7e5305320305eafb9b9
Publikováno v:
MCSoC
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) for bisynchronous communication channels. Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5bed522c8860595a39c65ada67825cac
https://doi.org/10.1109/mcsoc.2012.13
https://doi.org/10.1109/mcsoc.2012.13
Publikováno v:
IGCC
The increasingly parallel landscape of embedded computing platforms is bringing the reliability concern for the on-chip interconnection network (NoC) to the forefront.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f0d747c898063b959fa594db2b41b538
https://doi.org/10.1109/igcc.2012.6322281
https://doi.org/10.1109/igcc.2012.6322281
Autor:
L. Di Gregorio, Frank Olaf Sem-Jacobsen, Tobias Bjerregaard, Federico Angiolini, Federico Silla, Davide Bertozzi, Alessandro Strano, Jose Flich, V. Todorov
Publikováno v:
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop.
The NaNoC project is progressing toward an innovative design platform for multicore systems based on future networks-on-chip. This platform enables the design, manufacturing and management of networks-on-chip by tackling new requirements of future sy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::93f8ad39f50d6f61ae7eb3efa5dd160d
https://doi.org/10.1145/2107763.2107775
https://doi.org/10.1145/2107763.2107775