Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Alberto Garcia-Oritz"'
Publikováno v:
ICCD
For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application model and technology parameters. In conventional methods, the two inpu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5f40f1b184d2f1c41c6d24171f7bbe3b
https://doi.org/10.1109/iccd46524.2019.00064
https://doi.org/10.1109/iccd46524.2019.00064
Autor:
Dominik Ermel, Tobias Drewes, Jan Moritz Joseph, Alberto Garcia-Oritz, Lennart Bamberg, Thilo Pionteck
Publikováno v:
MOCAST
Linear models are regularly used for mapping cores to tiles in a chip. System-on-Chip (SoC) design requires integration of functional units with varying sizes, but conventional models only account for identical-sized cores. Linear models cannot calcu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d63a2fc88fb402a0f1f876b47ccceeb7
Autor:
Imad Hajjar, Lennart Bamberg, Thilo Pionteck, Gerald Krell, Jan Moritz Joseph, Alberto Garcia-Oritz
Publikováno v:
ReCoSoC
3D heterogeneous integration poses new requirements to the modeling of interconnection networks. Traditional simulation models for Networks-on-Chip (NoCs) cover neither asymmetric components nor heterogeneous integration. Generic decomposition of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4f6881bc30e5472ab9c4a0bd3c42832
https://doi.org/10.1109/recosoc.2018.8449387
https://doi.org/10.1109/recosoc.2018.8449387
Publikováno v:
ReCoSoC
We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75a6b184fe82207a40b931375541152b
https://doi.org/10.1109/recosoc.2016.7533908
https://doi.org/10.1109/recosoc.2016.7533908
Publikováno v:
Technologies, Vol 8, Iss 1, p 10 (2020)
Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the core
Externí odkaz:
https://doaj.org/article/238e830993ae4f5093ad06e6df464ef7