Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Albert M. Chu"'
Publikováno v:
IEEE Transactions on Electron Devices. 69:7135-7140
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4812084cd2938cfdf9b5206b492852fa
https://doi.org/10.1109/ted.2022.3216975
https://doi.org/10.1109/ted.2022.3216975
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:60-67
We assess the performance impact of cobalt interconnect metallization for both signal routing and power delivery in advanced logic technologies with a minimum metal pitch of 32 nm or less. While cobalt interconnects may enable lower line resistance i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e033e0153566ac33a8f906657e8e509e
https://doi.org/10.1109/tvlsi.2021.3126541
https://doi.org/10.1109/tvlsi.2021.3126541
Publikováno v:
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
New device architectures such as horizontal Nanosheets have been seriously considered as a replacement for FinFET. A comprehensive, and realistic assessment of these architectures at the early stages of technology development is indispensable to unde
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b28af4c6e64493527f5d4db5d8afd37
https://doi.org/10.1109/sispad.2018.8551699
https://doi.org/10.1109/sispad.2018.8551699
Autor:
T. Hook, Lars W. Liebmann, Sungkweon Baek, R. Sengupta, Edward J. Nowak, Myung-Hee Na, Albert M. Young, Y. M. Lee, Albert M. Chu, H. Trombley, Xin Miao
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realizati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3b6fe403f2a0a626bd1f5364358dc91
https://doi.org/10.1109/iedm.2017.8268474
https://doi.org/10.1109/iedm.2017.8268474
Publikováno v:
SPIE Proceedings.
This paper reviews the most critical components of a ‘holistic’ DTCO flow for an advanced technology node and in doing so quantifies the differences between 7nm technology node definitions implemented with extreme ultraviolet and 193nm immersion
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af14c1458b31bde642c2af2130b3ae8c
https://doi.org/10.1117/12.2175509
https://doi.org/10.1117/12.2175509
Autor:
P. Andrew Scott, John George Petrovick, Keith M. Carrig, Frank D. Ferraiolo, Richard J. Weiss, Albert M. Chu
Publikováno v:
The Journal of VLSI Signal Processing. 16:217-224
This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f630fb3278a66b9a134f6236d48a526c
https://doi.org/10.1023/a:1007999209786
https://doi.org/10.1023/a:1007999209786
Publikováno v:
High Performance Clock Distribution Networks ISBN: 9781468484427
This paper discusses an effective clock methodology for the design of a high-performance microprocessor. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c00718d007225e67751afcaf7e96a35
https://doi.org/10.1007/978-1-4684-8440-3_9
https://doi.org/10.1007/978-1-4684-8440-3_9
Autor:
John George Petrovick, V. Girardi, Alvar A. Dean, Keith M. Carrig, R. Weiss, P. A. Scott, G. Rodgers, M. Murphy, K. Carpenter, Frank D. Ferraiolo, Y. Lapid, Allan Robert Bertolet, D. Willmott, T. Decker, S. Kenyon, D. Phan, Albert M. Chu, T. Bairley
Publikováno v:
ISPD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3a640785ac6ddbc33f83c300d085de7
https://doi.org/10.1145/267665.267702
https://doi.org/10.1145/267665.267702
Autor:
L. Pastel, Frank Ray Keyser, G. Richardson, C. LaMarche, R. Taylor, Allan Robert Bertolet, Brian A. Worth, Albert M. Chu, T. Harroun, John George Petrovick
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
A 300 K-circuit ASIC (application-specific-integrated-circuit) family built in a 0.8- mu m four-level-metal single-poly CMOS process is discussed. Wafers consist of p/sup +/ substrate with a p-epitaxial layer and retrograde n-wells. Polysilicon and d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0089942960f1f834fc214e6464675178
https://doi.org/10.1109/isscc.1990.110142
https://doi.org/10.1109/isscc.1990.110142
Conference
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