Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Alan J. Leslie"'
Publikováno v:
SPIE Proceedings.
A heuristic optimization approach has been developed to optimize SRAF (sub resolution assist feature) placement rules for advanced technology nodes by using a genetic algorithm. This approach has demonstrated the capability to optimize a rule-based S
Autor:
Anuja De Silva, Shayak Banerjee, Alan J. Leslie, Kisup Chung, Hong Kry, Ranee Kwong, Dongbing Shao, Bidan Zhang, Yea-Sen Lin
Publikováno v:
SPIE Proceedings.
Challenges in block levels due to the dilemma of cost control and under-layer effects have been addressed in several papers already, and different approaches to solve the issue have been addressed. Among the known approaches, developable BARC and und
Autor:
Alan J. Leslie, Robert Heiland
Publikováno v:
Microelectronic Engineering. 24:51-58
The increasing complexity of todays integrated circuits (IC's) results sometimes in physical restrictions for electron beam probing. Measurements on passivated structures as well as on buried layers are impeding the voltage accuracy and leading to in
Publikováno v:
SPIE Proceedings.
Model based optical proximity correction (MB-OPC) is essen tial for the production of advanced integrated circuits (ICs). As the speed and functionality requirements of IC production necessitate continual reduction of the critical dimension (CD), the
Autor:
Chandrasekharan Kothandaraman, Alan J. Leslie, Deok-kee Kim, Gregory J. Fredeman, Dan Moy, Xiang Chen, Alberto Cestero, John M. Safran, T. Kirihata, Yan Zun Li, R. Rajeevakumar, Norman Robson, S. S. Iyer
Publikováno v:
2007 IEEE Symposium on VLSI Circuits.
Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65
Autor:
Norman Robson, Alberto Cestero, Alan J. Leslie, Chandrasekharan Kothandaraman, Dan Moy, R. Rajeevakumar, John M. Safran, Xiang Chen, Subramanian S. Iyer, T. Kirihata
Publikováno v:
CICC
Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy, chip identification and authentication, analog device trimming, and other applications. We will review the evolution and applications of electrical fuse solutions for 18
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
Autor:
Thomas Schafbauer, S. Sportouch, Baozhen Li, Pak Leung, Y. H. Lin, Yi-Cheng Chen, Yimin Huang, Phung T. Nguyen, Chuan Lin, Shih-Fen Huang, Ming-Tsan Lee, A. Olbrich, Philipp Riess, J. Brighten, G. Knoblinger, Andy Cowley, U. Hodel, A. Grassmann, W. Nissl, Dirk Vietzke, Kun-Chi Lin, Larry Clevenger, Kai Esmark, Robert C. Wong, Hsiang-Jen Huang, C. Wann, M. Commons, Alan J. Leslie, T. Schiml, Martin Wendel, Qiuyi Ye, Erdem Kaltalioglu, Nivo Rovedo, Alvin G. Thomas
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful inte
Publikováno v:
1995 Proceedings. 45th Electronic Components and Technology Conference.
The presence of a copper oxide layer on the leadframe of plastic IC packages was found to cause delamination at the diepad/mold compound interface. The failure mechanism seems to be the presence of voids at the oxide/metal interface, which increased
Autor:
E. Hsiung, Terry A. Spooner, G. Brase, Erdem Kaltalioglu, F. Grellner, Mark Hoinkis, B. von Ehrenwall, D. Warner, Klaus Schruefer, T. Schiml, L. Burrell, Robert C. Wong, C. Wang, Thomas Schafbauer, A. Von Ehrenwall, Tobias Mono, P. Kim, G. Knoblinger, Fernando Guarin, K.C. Chen, Petra Felsner, Alan J. Leslie, Uwe Schroeder, S. Biesemans, E. Demm, Andy Cowley, J. Gill, L.K. Han, S. Kulkarni, P. Leung
Publikováno v:
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industry's first true low-k dielectric (SiLK, k=2.7) (G
Conference
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