Zobrazeno 1 - 10
of 319
pro vyhledávání: '"Al Davis"'
Publikováno v:
SC
In efforts to increase performance and reduce cost, modern low-diameter networks are designed for average case traffic and rely on non-minimal adaptive routing for network load-balancing when adversarial traffic patterns are encountered. Source adapt
Publikováno v:
Hot Chips Symposium
Publikováno v:
ISPASS
The interconnection networks of modern largescale computing systems are quickly increasing in size and complexity to keep up with the demand for computing capability. These systems rely heavily on complex router microarchitectures and intelligent ada
Autor:
Feifei Li, Al Davis, Vijayalakshmi Srinivasan, Seth H. Pugsley, Rajeev Balasubramonian, Alper Buyuktosunoglu, Jeffrey Jestes
Publikováno v:
IEEE Micro. 34:44-52
The emergence of 3D stacking and the imminent release of Micron's Hybrid Memory Cube (HMC) device have made it more practical to move computation near memory. This work presents a detailed analysis of in-memory MapReduce in the context of near-data c
Publikováno v:
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
Publikováno v:
ISCA
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a large number of chips on every memory access -- this increases energy co
Autor:
Norm Jouppi, Robert Schreiber, Al Davis, Nathan Binkert, Naveen Muralimanohar, Moray McLaren, Jung Ho Ahn
Publikováno v:
IEEE Micro. 32:100-109
Networking consumes up to 33 percent of modern data center power. Network switches are the key source of inefficiency: a switch traversal costs an order of magnitude more than a link traversal. The authors propose a new high-radix switch architecture
Publikováno v:
International Journal of Parallel Programming. 40:57-83
Modern processors such as Tilera’s Tile64, Intel’s Nehalem, and AMD’s Opteron are migrating memory controllers (MCs) on-chip, while maintaining a large, flat memory address space. This trend to utilize multiple MCs will likely continue and a co
Autor:
Moray McLaren, Jung Ho Ahn, Norman P. Jouppi, Naveen Muralimanohar, Robert Schreiber, Al Davis, Nathan Binkert
Publikováno v:
ISCA
For large-scale networks, high-radix switches reduce hop and switch count, which decreases latency and power. The ITRS projections for signal-pin count and per-pin bandwidth are nearly flat over the next decade, so increased radix in electronic switc
Autor:
Rajeev Balasubramonian, Naveen Muralimanohar, Norman P. Jouppi, Niladrish Chatterjee, Aniruddha N. Udipi, Al Davis
Publikováno v:
ISCA
DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single request activates thousands of bit-lines in many DRAM chips