Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Akshat Chitransh"'
Autor:
Anumita Sengupta, Santashraya Prasad, Aminul Islam, Akshat Chitransh, Anushruti Priya, Shreya Moonka
Publikováno v:
2017 Devices for Integrated Circuit (DevIC).
In this paper, we have analyzed the DC & RF performance of a Pseudomorphic high electron mobility transistor (PHEMT) with an Al 0.22 Ga 0.78 As supply layer, In 0.18 Ga 0.82 As channel layer built on a p-type GaAs. Output characteristics curve (I d -
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e3607a7b8cccaf3057cd19673213fcc
https://doi.org/10.1109/devic.2017.8073969
https://doi.org/10.1109/devic.2017.8073969
Autor:
Anumita Sengupta, Shreya Moonka, Aminul Islam, Anushruti Priya, Santashraya Prasad, Akshat Chitransh
Publikováno v:
2017 Devices for Integrated Circuit (DevIC).
This paper proposes a High Electron Mobility Transistor (HEMT) which analyzed using Silvaco ATLASTM Tools. The proposed device is an AlGaN/GaN HEMT with AlN acting as a spacer layer. The design also includes a field plated gate to increase the breakd
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b792e0b3f568b161ef89a38422975243
https://doi.org/10.1109/devic.2017.8073929
https://doi.org/10.1109/devic.2017.8073929
Autor:
Anumita Sengupta, Shreya Moonka, Santashraya Prasad, Anushruti Priya, Aminul Islam, Akshat Chitransh
Publikováno v:
2017 Devices for Integrated Circuit (DevIC).
A structure of AlGaN/AlN/GaN High Electron Mobility Transistor with surface passivation is proposed in this paper. AlN layer in the proposed structure acts as spacer layer in order to improve the Two Dimensional electron gas mobility formed at the Al
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d7fa5787012c99ebca118d46a61e972
https://doi.org/10.1109/devic.2017.8073970
https://doi.org/10.1109/devic.2017.8073970
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789811029981
This paper presents a novel analysis of a self-compensating, low-noise, low-power Phase-Locked-Loop circuit design implemented @ 45-nm technology node. The basic Phase-Locked-Loop (PLL) circuit prescribed in the literature comprises a Phase Detector
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b460fa85c1332791cb2f09af5bc2eb9
https://doi.org/10.1007/978-981-10-2999-8_30
https://doi.org/10.1007/978-981-10-2999-8_30
