Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Akiyuki Minami"'
Autor:
Akiyuki Minami, Kuniaki Yagi, Hidetsugu Uchida, Naoki Hatta, Motoki Kobayasi, Hideki Takagi, Toyokazu Sakata, Takamitsu Kawahara
Publikováno v:
Journal of the Japan Society for Precision Engineering. 83:833-836
Publikováno v:
Materials Science Forum. :1109-1112
Transistor performances of lateral and vertical 3C-SiC MOSFETs are investigated in the temperature range of 25 °C to 300 °C. Both types of MOSFETs operate up to 300 °C and the lateral MOSFETs possess peak channel mobility of more than 100 cm2/(Vs)
Autor:
Hidetsugu Uchida, Toyokazu Sakata, Adolf Schöner, Romain Esteve, Akiyuki Minami, Motoki Kobayashi
Publikováno v:
Materials Science Forum. :645-648
3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitri
Autor:
Yoshihisa Matsubara, Takashi Nasuno, Wataru Wakamiya, Eiichi Soda, N. Kobayashi, Akiyuki Minami, Hiroshi Tsuda, Hiromasa Kobayashi, Koichiro Tsujita
Publikováno v:
IEICE Transactions on Electronics. :796-803
A novel via chain structure for failure analysis at 65 nm-node fixing OPC using inner and outer via chain dummy patterns has been proposed. The inner dummy is necessary to localize failure site in 200 nm pitch via chain using an optical beam induced
Publikováno v:
Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials.
Publikováno v:
SPIE Proceedings.
We developed a process monitoring system that calculates the effective dose and focus of device wafers using an overlay metrology tool. The effective dose is monitored by measuring the overall width of the fine line-and-space (LS) patterns, the duty
Publikováno v:
SPIE Proceedings.
Pattern placement error (PPE) of device pattern and overlay mark does not necessarily coincide. So it is important to measure PPE of device pattern accurately for optimizing overlay mark design. But it has been hard. To resolve this problem a new met
Autor:
Takashi Nasuno, H. Aoyama, Wataru Wakamiya, Koichiro Tsujita, Hiroshi Tsuda, Yoshihisa Matsubara, N. Uchida, N. Kobayashi, Akiyuki Minami, Hiromasa Kobayashi
Publikováno v:
Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).
A new test structure for fixing OPC (optical proximity correction) is proposed in which inner and outer dummy patterns surrounding an electrically connected 200 nm-pitch via chain array are used. An unconnected outer dummy via chain is designed as a
Autor:
Naoki Hatta, Yuichi Kurashima, Takafumi Okuda, Kou Imaoka, Kuniaki Yagi, Hidetsugu Uchida, Hideki Takagi, Akiyuki Minami, Jun Suda, Takamitsu Kawahara, Toyokazu Sakata
Publikováno v:
ResearcherID
We have developed 100mm in diameter 4H-SiC/poly-SiC bonded wafer by SAB method. The SiC bonded wafer demonstrated an excellent thermal stability against device processing temperature. SBDs fabricated on the SiC bonded wafer exhibited good I-V charact
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