Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Akiko Nomachi"'
Autor:
Hiroshi Itokawa, Ichiro Mizushima, Atsushi Azuma, Hideaki Harakawa, T. Morooka, Akiko Nomachi, Fukushima Takashi, Nobutoshi Yasutake, L. Zhang, Y. Toyosihma
Publikováno v:
Solid-State Electronics. 53:694-700
This paper describes the fabrication process and device performance of complimentary metal oxide field effect transistor (CMOSFET) with direct silicon bonded (DSB) substrate. This works offers the first comprehensive evaluation of source/drain engine
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52f14529e9d375d25ff7c00baa2ea4f4
https://doi.org/10.1016/j.sse.2009.03.016
https://doi.org/10.1016/j.sse.2009.03.016
Autor:
Hiroshi Amitsuka, T. Tayama, Yoshichika Ōnuki, Toshiro Sakakibara, Kenichi Tenya, Kazuyuki Matsuhira, Kunihiko Maezawa, Akiko Nomachi
Publikováno v:
Journal of the Physical Society of Japan. 68:3402-3406
Simultaneous measurements of the magnetization M and the magnetostriction λ of a high quality single crystal of CeRu 2 Si 2 were performed at temperatures down to 70 mK in magnetic fields H up to 85 kOe, in order to test the validity of the scaling
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c653c8c900cf5d3481b5f26610b7965a
https://doi.org/10.1143/jpsj.68.3402
https://doi.org/10.1143/jpsj.68.3402
Autor:
Yoshiaki Toyoshima, Kiyomi Nakajima, H. Oguma, Masato Koyama, Koji Nagatomo, Shigeru Kawanaka, Kazuhiro Eguchi, Seiji Inumiya, Katsura Miyashita, T. Ishida, Satoshi Inaba, Hideaki Harakawa, Fukushima Takashi, Takayuki Aoyama, Kosuke Tatsumura, H. Onoda, Y. Yoshimizu, Masakazu Goto, Reika Ichihara, Akiko Nomachi, Atsushi Azuma, T. Sasaki
Publikováno v:
2008 Symposium on VLSI Technology.
We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aedbe132660f065f34d7bce937aae208
https://doi.org/10.1109/vlsit.2008.4588591
https://doi.org/10.1109/vlsit.2008.4588591
Autor:
Akiko Yamada, Shoji Mimotogi, Kotaro Fujii, Hiroki Yonemitsu, Akiko Nomachi, Tatsuhiko Ema, Shinichi Ito, Satoshi Nagai, Hiroharu Fujise, Yuriko Seino, Fukushima Takashi, Toshiaki Komukai, Koutarou Sho, Yosuke Kitamura, Tsukasa Azuma
Publikováno v:
Advances in Resist Materials and Processing Technology XXV.
Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The ta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f0225e7d02a33f8f394c13337d5ebd1
https://doi.org/10.1117/12.771008
https://doi.org/10.1117/12.771008
Autor:
Katsura Miyashita, Masaki Satake, Katsuyoshi Kodera, Soichi Inoue, Kazuhiro Takahata, Hideaki Harakawa, Yosuke Kitamura, Hiroharu Fujise, Shoji Mimotogi, Koutaro Sho, Tatsuya Ishida, Tatsuhiko Ema, Kenji Yoshida, Suigen Kyoh, Kazutaka Ishigo, Masafumi Asano, Hideki Kanai, Takuya Kono, Akiko Nomachi
Publikováno v:
Optical Microlithography XXI.
We have designed the lithography process for 32nm node logic devices under th e 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f963acc1eddb32aedb38f145a206a9b3
https://doi.org/10.1117/12.772201
https://doi.org/10.1117/12.772201
Comprehensive study of S/D engineering for 32 nm node CMOS in direct silicon bonded (DSB) technology
Autor:
Fukushima Takashi, Hideaki Harakawa, Atsushi Azuma, T. Morooka, Ichiro Mizushima, Hiroshi Itokawa, L. Zhang, Y. Toyosihma, Nobutoshi Yasutake, Akiko Nomachi
Publikováno v:
ESSDERC 2008 - 38th European Solid-State Device Research Conference.
This paper describes the fabrication process and device performance of CMOSFET with direct silicon bonded (DSB) substrate. This works offers the first comprehensive evaluation of source/drain engineering for DSB devices. Scanning spreading resistance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::506a854c2bb1c5a2ba2a3ef7fecc127f
https://doi.org/10.1109/essderc.2008.4681765
https://doi.org/10.1109/essderc.2008.4681765
Autor:
Atsushi Azuma, Hideaki Harakawa, Akiko Nomachi, Ichiro Mizushima, Hiroshi Itokawa, T. Ishida, Fukushima Takashi, Nobuaki Yasutake, Yoshimasa Kawase
Publikováno v:
ECS Meeting Abstracts. :645-645
Direct Silicon Bonded Si (DSB) technology with amorphization templated recrystallization process enables a relatively simple integration of CMOSFET using hybrid orientation bulk substrates. The absence of oxide at the bonding interface enables the ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::09cc6eb225ba2df0e7cc46b5f7f13b15
https://doi.org/10.1149/ma2008-01/16/645
https://doi.org/10.1149/ma2008-01/16/645