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pro vyhledávání: '"Ajay Kallianpur"'
Publikováno v:
VTS
Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a37bf70a35e190cae42686e51f50f9e
https://doi.org/10.1109/vts.2012.6231066
https://doi.org/10.1109/vts.2012.6231066
Publikováno v:
2012 IEEE 30th VLSI Test Symposium (VTS); 1/ 1/2012, p1-14, 14p
Autor:
Rao, Sushmita Kadiyala, Sathyanarayana, Chaitra, Kallianpur, Ajay, Robucci, Ryan, Patel, Chintan
Publikováno v:
2012 IEEE 30th VLSI Test Symposium (VTS); 1/ 1/2012, p276-281, 6p