Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Ahmed, MD Rubel"'
Scaling laws dictate that the performance of AI models is proportional to the amount of available data. Data augmentation is a promising solution to expanding the dataset size. Traditional approaches focused on augmentation using rotation, translatio
Externí odkaz:
http://arxiv.org/abs/2409.00547
High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly. However, exploring various design space paramet
Externí odkaz:
http://arxiv.org/abs/2403.10686
Modeling system-level behaviors of intricate System-on-Chip (SoC) designs is crucial for design analysis, testing, and validation. However, the complexity and volume of SoC traces pose significant challenges in this task. This paper proposes an appro
Externí odkaz:
http://arxiv.org/abs/2308.03523
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of such specifications are daunting tasks. We propose a disruptive method th
Externí odkaz:
http://arxiv.org/abs/2209.07929
Autor:
Ahmed, Md Rubel, Zheng, Hao
High-quality system-level message flow specifications can lead to comprehensive validation of system-on-chip (SoC) designs. We propose a disruptive method that utilizes an attention mechanism to produce accurate flow specifications from SoC IP commun
Externí odkaz:
http://arxiv.org/abs/2203.13182
Autor:
Ahmed, Md Rubel, Zheng, Hao
Publikováno v:
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
In this paper, we study seven well-known trace analysis techniques both from the hardware and software domain and discuss their performance on communication-centric system-on-chip (SoC) traces. SoC traces are usually huge in size and concurrent in na
Externí odkaz:
http://arxiv.org/abs/2103.10778
Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of inferring models from communication traces of system-on-chip~(SoC) designs. The traces capture
Externí odkaz:
http://arxiv.org/abs/2102.06989
Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify how components of an SoC design communicate and coordinate with each other to realize vario
Externí odkaz:
http://arxiv.org/abs/2005.11221
Akademický článek
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Publikováno v:
JSFA Reports; Oct2024, Vol. 4 Issue 10, p352-361, 10p
