Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Ah-Lyan Yee"'
Autor:
V. Gupta, Yiqun Xie, L. Dyson, R. Gu, Paul E. Landman, Bhavesh G. Bhakta, John Powers, W. Mohammed, Ah-Lyan Yee, K. Heragu, Wai Lee, Lin Wu, Mustafa Ulvi Erdogan, B. Parthasarathy, Keith Brouse, Robert Floyd Payne, Song Wu, Srinath Ramaswamy
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:2646-2657
A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2447560f09f9be5f8da0f41cb5ece132
https://doi.org/10.1109/jssc.2005.856583
https://doi.org/10.1109/jssc.2005.856583
Publikováno v:
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
A 6.25GHz PLL with integrated LC-tank VCO, on-chip loop filter and quadrature outputs is fabricated in 0.13mum CMOS technology. Operated at 1V supply with 62.5MHz input reference clock frequency, an output clock jitter of 0.5psrms is achieved by usin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dfdd385473cf3403e506dd87b002eb94
https://doi.org/10.1109/isscc.2006.1696308
https://doi.org/10.1109/isscc.2006.1696308
Autor:
Robert Floyd Payne, Bhavesh G. Bhakta, Ulvi Erdogan, Ah-Lyan Yee, Srinath Ramaswamy, L. Dyson, John Powers, B. Parthasarathy, Yiqun Xie, Lin Wu, Song Wu, R. Gu, Keith Brouse, W. Mohammed, Paul E. Landman, K. Heragu, Wai Lee, V. Gupta
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A transmit architecture with a programmable 4-tap feedforward equalizer for 6.25 to 12.5 Gb/s serial communications through lossy channels is described. A 16:8-channel MUX/DEMUX chip fabricated in a 0.13 /spl mu/m 7M CMOS process demonstrates a near-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15a38b7aef36a2961232cbd0ce92f5fd
https://doi.org/10.1109/isscc.2005.1493871
https://doi.org/10.1109/isscc.2005.1493871
Autor:
Keith Brouse, W. Mohammed, Bhavesh G. Bhakta, Ah-Lyan Yee, Song Wu, V. Gupta, B. Parthasarathy, Yiqun Xie, Srinath Ramaswamy, Paul E. Landman, Ulvi Erdogan, L. Dyson, Wai Lee, R. Gu, K. Heragu, John Powers, Robert Floyd Payne, Lin Wu
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb067ab133c08f8eb2cfbd2c055e3314
https://doi.org/10.1109/isscc.2005.1493872
https://doi.org/10.1109/isscc.2005.1493872
Autor:
P. Fremrot, L. Dyson, Wai Lee, Ah-Lyan Yee, M. Frannhagen, V. Gupta, Paul E. Landman, K. Lewis, P. Bosshart, S. Johansson, R. Gu, J. Reynolds, Srinath Ramaswamy, B. Parthasarathy
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6b0377b013af3a52e98238fe07fb7db2
https://doi.org/10.1109/isscc.2002.992944
https://doi.org/10.1109/isscc.2002.992944
Autor:
L. Dyson, Wai Lee, V. Gupta, Song Wu, Ah-Lyan Yee, Srinath Ramaswamy, R. Gu, B. Parthasarathy, Paul E. Landman
Publikováno v:
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
This paper describes I/O circuits that can be used in high-speed transceivers to communicate with next generation and legacy devices. We describe the transmitter and receiver front-end circuits that are designed to operate with dual termination volta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21bf136485164e18556b4a91aaab2162
https://doi.org/10.1109/vlsic.2002.1015049
https://doi.org/10.1109/vlsic.2002.1015049
Autor:
Ah-Lyan Yee, A. Tsong, V. Pathak, Martin J. Izzard, E. Suder, J.M. Tran, R. Prentice, R. Venett, S. Spencer, R. Gu, Heng-Chih-Lin
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
This paper describes a high speed, low jitter CMOS transceiver, which includes 10 to 1 full duplex serialize-deserialize function, clock recovery, high speed differential I/O, and Built In Self Test (BIST). It was fabricated and tested to work at wid
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85947ad9fa86945340e03474262ce97d
https://doi.org/10.1109/vlsic.1999.797230
https://doi.org/10.1109/vlsic.1999.797230
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
Fiber Channel networks, gigabit Ethernet backbones, and IEEE 1394.b Firewire links require a high-speed point-to-point connection. This CMOS serial link transceiver dissipates 250 mW and has low jitter (8ps RMS, 44 ps P-P at 3.5 Gb/s), and wide frequ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da73e2f11b1de1bb2315bb46eb5a9f5d
https://doi.org/10.1109/isscc.1999.759289
https://doi.org/10.1109/isscc.1999.759289
Publikováno v:
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers; 2006, p2442-2451, 10p
Autor:
Landman, P., Ah-Lyan Yee, Gu, R., Parthasarathy, B., Gupta, V., Ramaswamy, S., Dyson, L., Bosshart, P., Reynolds, J., Frannhagen, M., Fremrot, P., Johansson, S., Lewis, K., Wai Lee
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315); 2002, p52-398, 347p