A new technique for background calibration of pipelined ADCs.

Autor: Mohammadi, Meysam, Alipour, Amir, Aghdam, Esmaeil N., Sadeghipour, Khosrov D.

Publikováno v: 2013 21st Iranian Conference on Electrical Engineering (ICEE); 2013, p1-5, 5p

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Autor: Asgar Abbaszadeh, Alfredo Rosado-Muñoz, Esmaeil Najafi Aghdam

Publikováno v: Abbaszadeh, Asgar Aghdam, Esmaeil N. Rosado Muñoz, Alfredo 2019 Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC Analog Integrated Circuits and Signal Processing 99 2 299 310
RODERIC. Repositorio Institucional de la Universitat de Valéncia
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RODERIC: Repositorio Institucional de la Universitat de Valéncia

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved chann

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::db45e44837cd093830c3c9ac3df626e8
https://hdl.handle.net/10550/75703