Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Afran Sorwar"'
Autor:
Md. Ashik Zafar Dipto, Afran Sorwar, Muhtasim Alam Chowdhury, Md. Nayem, Marzia Akter Mona, Abdullah Al Asif
Publikováno v:
2021 International Conference on Computer Communication and Informatics (ICCCI).
Full Adder (FA) being an integral part of Arithmetic Logic Unit (ALU) of modern integrated circuits (IC) has gained massive research interest by academicians and industrial IC designers. Therefore, a large number of FA cell designs have been innovate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45d7be650ed2259d6a4bd351cea8c9d9
https://doi.org/10.1109/iccci50826.2021.9402506
https://doi.org/10.1109/iccci50826.2021.9402506
Publikováno v:
ICCCNT
Conventional static CMOS design employing pull-up and pull-down network for implementing logic functions has been one of the most reliable and widely used design techniques over the years. However, high input impedance and transistor count remains a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0953b08c5ea461326278e6be1979d61
https://doi.org/10.1109/icccnt49239.2020.9225667
https://doi.org/10.1109/icccnt49239.2020.9225667
Autor:
Afran Sorwar, Elias Ahammad Sojib, Md. Sabbir Alam Chowdhury, Md. Ashik Zafar Dipto, Abdul Hasib Siddique, Md. Mostak Tahmid Rangon
Publikováno v:
ICCCNT
Design of a 2-bit binary Magnitude Comparator (MC) is presented in this research. The proposed MC has been designed using Conventional CMOS (CCMOS) logic, Pass Transistor Logic (PTL). The design is simulated along with 5 other existing MC designs in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3edcaaf0f63a60d4e2cc7b642109b139
https://doi.org/10.1109/icccnt49239.2020.9225524
https://doi.org/10.1109/icccnt49239.2020.9225524
Autor:
Md. Ashik Zafar Dipto, Mehedi Hasan, Muhammad Saddam Hossain, Hasan U. Zaman, Afran Sorwar, Uttam Kumar Saha
Publikováno v:
ICCCNT
This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) logic. To test performance parameters, simulation has been conducted using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::662fd0c10ddc7ec5028c6f3b8d3f1eb9
https://doi.org/10.1109/icccnt45670.2019.8944888
https://doi.org/10.1109/icccnt45670.2019.8944888