Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Adrian Barredo"'
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal dissipation capabilities of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4769c12a21b6505363bf478acdaeab24
https://doi.org/10.1007/s11227-019-02841-6
https://doi.org/10.1007/s11227-019-02841-6
Autor:
Osman Unsal, Adrian Cristal, Miquel Moreto, Mateo Valero, Julian Pavon, Adrian Barredo, Joan Marimon, Francesc Moll, Ivan Vargas Valdivieso
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
HPCA
Universitat Politècnica de Catalunya (UPC)
HPCA
Sparse matrix operations are critical kernels in multiple application domains such as High Performance Computing, artificial intelligence and big data. Vector processing is widely used to improve performance on mathematical kernels with dense matrice
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c850b8164358dc01be4e4c5b31bc4e41
https://hdl.handle.net/2117/346406
https://hdl.handle.net/2117/346406
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Since the early 70s, simulation infrastructures have been a keystone in computer architecture research, providing a fast and reliable way to prototype and evaluate ideas for future computing systems. There are different types of simulators, from most
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7714cbcdac95bdb33ff27b4ded704664
http://hdl.handle.net/2117/329999
http://hdl.handle.net/2117/329999
Publikováno v:
PACT
Vector processing is a widely used technique to improve performance and energy efficiency in modern processors. Most of them rely on predication to support divergence control. However, performance and energy consumption in predicated instructions are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::431701683ad1795f0e32f6c509a4149c
https://doi.org/10.1109/pact.2019.00054
https://doi.org/10.1109/pact.2019.00054
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
PACT
Universitat Politècnica de Catalunya (UPC)
PACT
Development in process technology has led to an exponential increase in processor speed and memory capacity. However, memory latencies have not improved as dramatically and represent a well-known problem in computer architecture. Cache memories provi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::80e38cb35f2521d0542786dcbf4658c0
Autor:
Alberto Ros, Marc Casas, Thibaud Balem, Juan M. Cebrian, Miquel Moreto, Adrian Barredo, Alexandra Jimborean
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
DIGITUM. Depósito Digital Institucional de la Universidad de Murcia
instname
IEEE Transactions on Parallel and Distributed Systems (TPDS)
Universitat Politècnica de Catalunya (UPC)
DIGITUM. Depósito Digital Institucional de la Universidad de Murcia
instname
IEEE Transactions on Parallel and Distributed Systems (TPDS)
Vector processors (e.g., SIMD or GPUs) are ubiquitous in high performance systems. All the supercomputers in the world exploit data-level parallelism (DLP), for example by using single instructions to operate over several data elements. Improving vec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9fb2306de38b2d5b988f84d6d0e6a98a