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pro vyhledávání: '"Adit D. Singh"'
Publikováno v:
Journal of Electronic Testing. 38:235-246
Autor:
Adit D. Singh
Publikováno v:
2022 IEEE International Test Conference (ITC).
Publikováno v:
Journal of Electronic Testing. 37:41-63
Outsourcing of IC manufacturing has opened the possibility of intentionally modifying the operation of the IC in a subtle way so that it is extremely difficult to detect, in conventional functional testing. Security in computation is no longer a soft
Publikováno v:
Journal of Electronic Testing. 37:25-40
Recycling of used ICs as new replacement parts in maintaining older electronic systems is a serious reliability concern. This paper presents a novel approach to estimate the operational age of CMOS chips by measuring IDDQ, the quiescent current from
Publikováno v:
Journal of Electronic Testing. 36:301-311
A random number generator (RNG) is an important building block for cryptographic operations primarily to generate random nonces and secret keys. The power-up value of an SRAM array has been widely accepted as an entropy source for generating random n
Autor:
Sujay Pandey, Suriyaprakash Natarajan, Adit D. Singh, Zhiwei Liao, Arani Sinha, Abhijit Chatterjee, Shreyas Nandi
Publikováno v:
VTS
Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases in test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted b
Autor:
Paolo Bernardi, Matthias Sauer, Matteo Sonza Reorda, Adit D. Singh, Steffen Becker, Jens Anders, Ilia Polian, Krishnendu Chakrabarty, Nourhan Elhamawy, Stefan Wagner
System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge abo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a43ae95b1fb512c9dc911b6ee0dcca42
http://arxiv.org/abs/2103.06656
http://arxiv.org/abs/2103.06656
Autor:
Adit D. Singh, Suriyaprakash Natarajan, Zhiwei Liao, Arani Sinha, Abhijit Chatterjee, Sanya Gupta, Shreyas Nandi, Sujay Pandey
Publikováno v:
ITC
Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial res
Publikováno v:
VTS
The recycling of used integrated circuits (ICs) has raised serious problems in ensuring the integrity of today’s globalized semiconductor supply chain. This poses a serious threat to critical infrastructure due to potentially shorter lifetime, lowe
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37:2152-2165
Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today’s very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these de