Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Adin E. Hyslop"'
Autor:
Adin E. Hyslop, Joe W. McPherson, E.B. Smith, V.C. Huynh, R.A. Coy, Hugh P. McAdams, William R. McKee, N.Q. Nguyen, T.J. Aton, J.W. Janzen, D.E. Russell, D.W. Bergman, L.W. Block, J.C. Ondrusek
Publikováno v:
Proceedings of International Reliability Physics Symposium RELPHY-96.
The system soft error rate (SSER) of 4M/16M DRAMs has been shown to be dependent on the cosmic ray neutron flux. A simple model and accelerated soft error rate (ASER) measurements made with an intense, high energy neutron beam support this result. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::694920098487393a2e36df30a9b0d238
https://doi.org/10.1109/relphy.1996.492052
https://doi.org/10.1109/relphy.1996.492052
Autor:
Michael P. Duane, Michael C. Smayling, Mike Maekawa, Adin E. Hyslop, Dave Baglee, Charvaka Duvvury
Publikováno v:
Solid-State Electronics. 27:89-96
MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 μ m LDD devices with conventional devices of same channel length indicates t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6fffbd648b2f7a3f6f647b52ac454d53
https://doi.org/10.1016/0038-1101(84)90097-2
https://doi.org/10.1016/0038-1101(84)90097-2
Publikováno v:
24th International Reliability Physics Symposium.
The susceptibility of CMOS devices to latch-up becomes of greater concern as the spacing between geometries is reduced. An advanced 1 micron CMOS device is used to examine various methods of determining where on the device latch-up might occur. Two o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff77f7a4439ed308c6ea1899c25b9aed
https://doi.org/10.1109/irps.1986.362120
https://doi.org/10.1109/irps.1986.362120
Publikováno v:
25th International Reliability Physics Symposium.
Hot carrier stress degradation in MOSFETs is well known but its impact on DRAM circuit functionality has not been thoroughly investigated. In this paper observed DRAM degradation with stress is related to the actual transistor level degradation. It i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc15283d9a0ad987c9f0ee9d1caac1c6
https://doi.org/10.1109/irps.1987.362179
https://doi.org/10.1109/irps.1987.362179
Publikováno v:
IEE Journal on SolidState and Electron Devices. 2:138
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d84c2aa74c150721d457a101d214280
https://doi.org/10.1049/ij-ssed.1978.0047
https://doi.org/10.1049/ij-ssed.1978.0047
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