Zobrazeno 1 - 10
of 71
pro vyhledávání: '"Adegbija, Tosiron"'
Publikováno v:
IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2024)
Spiking Neural Networks (SNNs) are inspired by the sparse and event-driven nature of biological neural processing, and offer the potential for ultra-low-power artificial intelligence. However, realizing their efficiency benefits requires specialized
Externí odkaz:
http://arxiv.org/abs/2408.14437
Many modern embedded systems have end-to-end (EtoE) latency constraints that necessitate precise timing to ensure high reliability and functional correctness. The combination of High-Level Synthesis (HLS) and Design Space Exploration (DSE) enables th
Externí odkaz:
http://arxiv.org/abs/2408.10431
The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS pro
Externí odkaz:
http://arxiv.org/abs/2408.10428
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 9, pp. 1615-1629, Sept. 2024
In-memory computing promises to overcome the von Neumann bottleneck in computer systems by performing computations directly within the memory. Previous research has suggested using Spin-Transfer Torque RAM (STT-RAM) for in-memory computing due to its
Externí odkaz:
http://arxiv.org/abs/2407.19637
Processing-in-cache (PiC) and Processing-in-memory (PiM) architectures, especially those utilizing bit-line computing, offer promising solutions to mitigate data movement bottlenecks within the memory hierarchy. While previous studies have explored t
Externí odkaz:
http://arxiv.org/abs/2407.19627
Autor:
Gajaria, Dhruv, Adegbija, Tosiron
Publikováno v:
Proceedings of the international symposium on memory systems, pp. 439-450. 2019
Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM's write energy and latency overheads. Given a relaxed retention time STT-RAM level one (L1) cache, we analyze the impacts of dynamic
Externí odkaz:
http://arxiv.org/abs/2407.19612
Publikováno v:
2019 Tenth International Green and Sustainable Computing Conference (IGSC), Alexandria, VA, USA, 2019, pp. 1-7
Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times,
Externí odkaz:
http://arxiv.org/abs/2407.19604
High-level synthesis (HLS) has significantly advanced the automation of digital circuits design, yet the need for expertise and time in pragma tuning remains challenging. Existing solutions for the design space exploration (DSE) adopt either heuristi
Externí odkaz:
http://arxiv.org/abs/2407.08797
Publikováno v:
Sustainable Computing: Informatics and Systems 35 (2022): 100741
Embedded systems continue to rapidly proliferate in diverse fields, including medical devices, autonomous vehicles, and more generally, the Internet of Things (IoT). Many embedded systems require application-specific hardware components to meet preci
Externí odkaz:
http://arxiv.org/abs/2404.14769
High-Level Synthesis (HLS) Design Space Exploration (DSE) is a widely accepted approach for efficiently exploring Pareto-optimal and optimal hardware solutions during the HLS process. Several HLS benchmarks and datasets are available for the research
Externí odkaz:
http://arxiv.org/abs/2404.14754