Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Adam R. Waite"'
Autor:
Yash Patel, Joshua Baur, Jonathan Scholl, Adam R. Waite, Adam Kimura, John Kelley, Richard Ott, Glen David Via
Publikováno v:
EDFA Technical Articles. 23:4-13
Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on
Publikováno v:
EDFA Technical Articles. 23:12-18
Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article prese
Autor:
Eric Udelhoven, Joshua Baur, Adam R. Waite, Daniel Brooks, John Kelley, Yash Patel, Richard Ott, Jon Scholl, Glen D. Via, Adam G. Kimura
This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5f134dd8b0b6196cf1a1d4a3926447c9
https://doi.org/10.36227/techrxiv.15182256
https://doi.org/10.36227/techrxiv.15182256
Autor:
Joshua Baur, Adam G. Kimura, Adam R. Waite, Jonathan Scholl, John Kelley, Yash Patel, Glen D. Via
Publikováno v:
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE).
This paper reviews different methods for mounting and integrated circuit (IC) for delayering. In this work, several 130nm technology devices are observed during the delayering process as a means of evaluating the advantages and disadvantages of vario
Publikováno v:
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE).
This paper reviews the decomposition of a fabricated Serial Peripheral Interface (SPI) that was manufactured in a 130 nm process node technology to establish a verification and validation methodology for baselining microelectronics assurance. The fab
Publikováno v:
International Symposium for Testing and Failure Analysis.
This paper presents an in-depth review of the critical front end stages of the fabricated integrated circuit (IC) assurance workflow used for recovering the design stack-up of a fabricated IC. In this work, a Serial Peripheral Interface (SPI) embedde
Publikováno v:
Thin Solid Films. 649:177-186
The control of ultra-thin MoS2 film growth via annealing of thin film MoO3 precursor films was investigated. Through analysis by X-ray diffraction, Raman spectroscopy, and scanning electron microscopy, it was demonstrated that there is significant co
Autor:
John E. Bultman, Jamie J. Gengler, Christopher Muratore, Nicholas R. Glavin, Adam R. Waite, Timothy S. Fisher, Andrey A. Voevodin, Jianjun Hu
Publikováno v:
Surface and Coatings Technology. 397:126017
To combat the ever-increasing challenge of thermal management in nanoelectronic devices and reduce the risk of overheating during operation, material interfaces near the active region of a device must be designed for efficient thermal transport. In t
Publikováno v:
Surface and Coatings Technology. 280:260-267
Plasma assisted physical vapor deposition processes can provide alternative and scalable approaches for synthesis of two-dimensional (2D) materials. While plasma species with high kinetic energies and chemical activities are beneficial for reduced te
Publikováno v:
Surface and Coatings Technology. 201:4040-4045
This paper investigates the use of advanced triggering to synchronize a pulsed laser ablated plasma from a ceramic target with a pulsed DC sputtering plasma from a metal target for the purposes of depositing nanocomposite thin-films at low substrate