Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Adam Neale"'
Publikováno v:
Journal of Building Performance Simulation. 15:735-756
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:3265-3278
This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical
Publikováno v:
Journal of Building Performance Simulation. 13:583-605
Existing electricity smart meter data sets lack sufficient details on building parameters to evaluate the impact that home characteristics can have on electricity consumption. An extensive, open-source virtual smart meter (VSM) data set with correspo
Autor:
N. Seifert, Adam Neale
Publikováno v:
IEEE Transactions on Nuclear Science. 67:15-21
A chip-level single-event latchup (SEL) estimation methodology is introduced, and its accuracy is demonstrated on the test vehicles manufactured in a state-of-the-art technology for various process options. Novel test structures have been designed an
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:2519-2532
Sense amplifier (SA) input-referred offset often dictates the minimum required differential input ( $\Delta V_{\textrm {BL-min}}$ ) and is an important factor in realizing low-voltage static random access memories. This paper presents a HYbrid latch-
Publikováno v:
Energy and Buildings. 258:111823
Publikováno v:
2012 ASEE Annual Conference & Exposition Proceedings.
Publikováno v:
Building Simulation Conference proceedings.
Publikováno v:
IRPS
We report on pulsed laser and high-energy proton induced Single Event Latchup (SEL) testing. Arrayed Silicon Controlled Rectifier (SCR) structures that implement various different layout design styles relevant to SEL have been designed and fabricated
Autor:
Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao
Publikováno v:
IRPS
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high