Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Adam C. Cabe"'
Autor:
Stuart N. Wooters, Randy W. Mann, Mircea R. Stan, Travis N. Blalock, Zhenyu Qi, Adam C. Cabe, Jiajing Wang, Benton H. Calhoun
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1974-1985
Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3f43303ff8d4afe2101573314ca6611
https://doi.org/10.1109/tvlsi.2011.2168246
https://doi.org/10.1109/tvlsi.2011.2168246
Autor:
Mircea R. Stan, Adam C. Cabe
Publikováno v:
ACM Great Lakes Symposium on VLSI
Voltage stacking has been proposed as an efficient solution for power delivery in high performance processors, for 3D ICs, for pin-limited ICs, and for implicit sleep mode (standby) DC/DC conversion. In this paper we demonstrate voltage stacking for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::756ba2fe788c686702eab629489b1ccd
https://doi.org/10.1145/1973009.1973093
https://doi.org/10.1145/1973009.1973093
Publikováno v:
DAC
On-chip SRAM caches have come to dominate the total chip area and leakage power consumed in state-of-the-art microprocessor designs. Such large memories are necessary to attain high performance, however it is critical to minimize the idle currents dr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6982eb33ec8692bd84c13b84bb8758fd
https://doi.org/10.1145/1837274.1837451
https://doi.org/10.1145/1837274.1837451
Publikováno v:
Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon).
A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350nm and 65nm, using a sc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a208bc1ba0f99d56ce405a9cfeea5e5
https://doi.org/10.1109/secon.2010.5453930
https://doi.org/10.1109/secon.2010.5453930
Autor:
Shamik Das, Adam C Cabe
Publikováno v:
Nanotechnology. 20(16)
This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nanoelectronic processor systems based upon the field-programmable nanowire interconnect (FPNI) architecture. To evaluate this architecture, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5e296e0eb0e5842fcb871d1f1d45ab63
https://pubmed.ncbi.nlm.nih.gov/19420565
https://pubmed.ncbi.nlm.nih.gov/19420565
Publikováno v:
ISQED
On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfa921827b7c4babf30a3bc7f8834241
https://doi.org/10.1109/isqed.2009.4810261
https://doi.org/10.1109/isqed.2009.4810261
Publikováno v:
MSE
In the fast paced world of IC design, companies strive for ways to create competitive, robust designs, while delivering speedy time-to-market results. A top-down design flow provides a fast, results oriented design methodology, but, at most Universit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94593f566c2fca7b4b6d2acb03dac6b2
https://doi.org/10.1109/mse.2007.84
https://doi.org/10.1109/mse.2007.84
Publikováno v:
SoCC
Power and thermal considerations are becoming limiting factors for SoC designs as technology scales down. In this paper, a design methodology targeting a low-power and temperature-aware system is proposed. Dynamic voltage scaling (DVS) and dynamic th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c36ed9225085a76b8db8874cf0dcbcd4
https://doi.org/10.1109/socc.2006.283860
https://doi.org/10.1109/socc.2006.283860
Autor:
James M. Tour, Garrett S. Rose, Lloyd R. Harriott, Nabanita Majumdar, Yuxing Yao, John C. Bean, Mircea R. Stan, Nadine Gergel-Hackett, Adam C. Cabe
Publikováno v:
ACM Great Lakes Symposium on VLSI
In recent years many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This paper describes the challenges faced in building crossbar arr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca594bae605e3b11b486a8dd90e5a020
https://doi.org/10.1145/1127908.1127912
https://doi.org/10.1145/1127908.1127912
Autor:
Adam C. Cabe, Lloyd R. Harriott, Nadine Gergel-Hackett, James M. Tour, Nabanita Majumdar, Mircea R. Stan, Garrett S. Rose, John C. Bean, Yuxing Yao
Publikováno v:
ACM Journal on Emerging Technologies in Computing Systems. 3:3
In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95322a960f34237d510d4a46e90b0cfc
https://doi.org/10.1145/1229175.1229178
https://doi.org/10.1145/1229175.1229178